Ss Status Register (Sssr) - Renesas H8SX/1520 Series Hardware Manual

14.3.5

SS Status Register (SSSR)

SSSR is a status flag register for interrupts.
Bit
Bit Name
Initial Value
R/W
Bit Bit Name

7
6 ORER

5, 4
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7 6 5
— ORER —
0 0 0
R/W R/W
R/W
Initial
Value R/W

0
0 R/W
All 0 R/W
Section 14 Synchronous Serial Communication Unit (SSU)
4 3
— TEND
0 0
R/W R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Overrun Error
If the next data is received while RDRF = 1, an overrun
error occurs, indicating abnormal termination. SSRDR
stores 1-frame receive data before an overrun error
occurs and loses data to be received later. While ORER
= 1, consecutive serial reception cannot be continued.
Serial transmission cannot be continued, either.
[Setting condition]
When one byte of the next reception is completed with
RDRF = 1
[Clearing condition]
When writing 0 after reading ORER = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Mar. 14, 2006 Page 519 of 804
2 1
TDRE RDRF CE
1 0
R/W R/W R/W
REJ09B0104-0300
0
0