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3.2.7 Line status register
This register (LSR: 5000_0018H (UART0), 5001_0018H (UART1), 5002_0018H (UART2)) is used to check the
status of transmission and reception.
15
14
7
6
Error in
TEMT
Receiver FIFO
Name
R/W
Reserved
R
Error in Receiver FIFO
R
TEMT
R
THRE
R
BI *
R
CHAPTER 3 REGISTERS
13
12
Reserved
5
4
THRE
BI
Bit
After Reset
15:8
0
Reserved. When these bits are read, 0 is returned for each bit.
7
0
A zero is always read from this bit in non-FIFO mode.
This bit is set to "1" when a break interrupt error, parity error, or framing
error occurs in data read from the receive FIFO in FIFO mode. Reading
this register clears this bit to "0".
6
1
This bit is set to "1" when the transmit buffer (the THR register or transmit
FIFO) and transmit shift register (TSR) empty. This bit is cleared to "0"
when data is written to the transmit buffer or transmit shift register.
5
1
This bit is set to "1" when the transmit buffer (THR register or transmit
FIFO) empties.
This bit is cleared to "0" when at least 1 byte of data is written to the
transmit buffer.
4
0
This bit is set to "1" when a break interrupt occurs. Reading this register
clears this bit to "0".
A break interrupt is detected when a low level signal is received for 1 frame
or longer (for the total of the start bit, data stop bit, and stop bit).
When a start bit (low level) is detected, the receive block assumes that data
has been sent, and receives the data.
While a break interrupt is being acknowledged (a low level signal is being
input), the receive block continues to receive all zeros. (Reception stops
when an overrun occurs.)
In FIFO mode, the break interrupt information is stored in the receive FIFO
with all-0 data. A break interrupt is detected when the data is read.
Caution A framing error always occurs when a break interrupt is
User's Manual S19262EJ3V0UM
11
10
3
2
FE
PE
Function
detected. A parity error might occur, depending on the
settings of bits 5 to 3 of the LCR register.
9
8
1
0
OE
DR
(1/2)
25
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