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Figure 7-7. DMA Channel Control Registers 0 to 3 (DCHC0 to DCHC3) (2/2)
Bit position
Bit name
0
ENn
Remark
n = 0 to 3
7.5.6 DMA disable status register (DDIS)
This register maintains the contents of the ENn bit of the DCHCn register when an IDMASTP signal is input (n = 0
to 3).
This register is read-only in 8-bit or 1-bit units.
7
6
DDIS
0
0
Bit position
Bit name
3 to 0
CH3 to
CH0
Caution Bits 7 to 4 of the DDIS register must be set to 0. The operation when these bits are set to 1 is
not guaranteed.
Remark
n = 0 to 3
160
CHAPTER 7 DMAC
Sets whether DMA transfer is enabled or disabled for DMA channel n. This bit is cleared (0)
when the DMA transfer is completed. It is also cleared (0) when an IDMASTP signal is input or
when transfer is forcibly terminated by setting (1) the INITn bit.
0: DMA transfer is disabled
1: DMA transfer is enabled
Figure 7-8. DMA Disable Status Register (DDIS)
5
4
0
0
CH3
Reflects the contents of the ENn bit of the DCHCn register when an IDMASTP signal is input.
The contents of this register are maintained until the next IDMASTP signal is input or a system
reset occurs.
Preliminary User's Manual A14874EJ3V0UM
Function
3
2
1
CH2
CH1
Function
0
Address
After reset
CH0
FFFFF0F0H
00H
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