ST STM32L4+ Series Reference Manual page 1330

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.
•
Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
–
–
•
The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to
write the counter while it is running.
38.3.10 Asymmetric PWM mode
Asymmetric mode allows two center-aligned PWM signals to be generated with a
programmable phase shift. While the frequency is determined by the value of the
TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of
TIMx_CCRx registers. One register controls the PWM during up-counting, the second
during down counting, so that PWM is adjusted every half PWM cycle:
•
OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2
•
OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4
Asymmetric PWM mode can be selected independently on two channels (one OCx output
per pair of CCR registers) by writing '1110' (Asymmetric PWM mode 1) or '1111'
(Asymmetric PWM mode 2) in the OCxM bits in the TIMx_CCMRx register.
Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant
bit is not contiguous with the 3 least significant ones.
When a given channel is used as asymmetric PWM channel, its secondary channel can also
be used. For instance, if an OC1REFC signal is generated on channel 1 (Asymmetric PWM
mode 1), it is possible to output either the OC2REF signal on channel 2, or an OC2REFC
signal resulting from asymmetric PWM mode 2.
Figure 376
mode (channels 1 to 4 are configured in Asymmetric PWM mode 1).
Figure 376. Generation of 2 phase-shifted PWM signals with 50% duty cycle
Counter register
OC1REFC
CCR1=0
CCR2=8
OC3REFC
CCR3=3
CCR4=5
1330/2301
The direction is not updated if a value greater than the auto-reload value is written
in the counter (TIMx_CNT>TIMx_ARR). For example, if the counter was counting
up, it continues to count up.
The direction is updated if 0 or the TIMx_ARR value is written in the counter but no
Update Event UEV is generated.
shows an example of signals that can be generated using Asymmetric PWM
0 1 2 3 4 5 6 7 8
RM0432 Rev 6
7 6 5 4 3 2
RM0432
1 1 0 1
MS33117V1