ST STM32L4+ Series Reference Manual page 1333

RM0432
Figure 378
for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in
PWM mode.
Counter (CNT)
(OCxCE = '0')
(OCxCE = '1')
Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the
next counter overflow.
shows the behavior of the OCxREF signal when the ETRF input becomes high,
Figure 378. Clearing TIMx OCxREF
(CCRx)
ETRF
OCxREF
OCxREF
General-purpose timers (TIM2/TIM3/TIM4/TIM5)
ocref_clr_int ocref_clr_int
becomes high
RM0432 Rev 6
still high
MS33105V2
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