Renesas RZ/G1E User Manual
  1. Manuals
  2. Brands
  3. Renesas Manuals
  4. Computer Hardware
  5. RZ/G1E
  6. User manual

Renesas RZ/G1E User Manual

For rich graphics applications rz/g series arm, specifications of individual rz/g series product
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
RZ/G1E
for Rich Graphics Applications
RZ/G Series
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp.
User's Manual: Hardware
Specifications of Individual RZ/G Series Product
Rev.1.00 Sep 2016

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the RZ/G1E and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Renesas RZ/G1E

Summary of Contents for Renesas RZ/G1E

  • Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp.
  • Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
  • Page 3 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
  • Page 4 Make sure to refer to the latest versions of these documents. Document Type Description Document Title Document No. User’s manual Overview of hardware, pin assignments, pin RZ/G1E User’s Manual: R01UH0544EJ0 for specifications multiplexing, and pin function controller Hardware 100 Rev.1.00 of individual (This user’s...
  • Page 5 3. Register Notation Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. All trademarks and registered trademarks are the property of their respective owners.

  • Page 6: Table Of Contents

    Contents 1. Overview ............................1-1 Introduction ................................1-1 System Configuration Diagram..........................1-2 List of Specifications ............................. 1-3 1.3.1 ARM Core ..............................1-3 1.3.2 CPU Core Peripherals ..........................1-4 1.3.3 External Bus Module ........................... 1-5 1.3.4 Internal Bus Module ............................ 1-7 1.3.5 Local Memory .............................
  • Page 7 5.3.15 Peripheral Function Select Register 6 (IPSR6) ..................5-25 5.3.16 Peripheral Function Select Register 7 (IPSR7) ..................5-26 5.3.17 Peripheral Function Select Register 8 (IPSR8) ..................5-27 5.3.18 Peripheral Function Select Register 9 (IPSR9) ..................5-28 5.3.19 Peripheral Function Select Register 10 (IPSR10) ..................5-29 5.3.20 Peripheral Function Select Register 11 (IPSR11) ..................

  • Page 8: Overview

    • CAN interface. Also, a full implementation of the extremely expandable and Internal AXI bus has been adopted for the RZ/G1E. This bus structure is optimized for maximum system performance, leading to the realization of high-performance and cost-effective premium in-vehicle infotainment systems.

  • Page 9: System Configuration Diagram

    Secure up- time clock Quad-SPI HSCIF (3 ch) DTCP (1 ch) (7 ch) DDR3- Gyro ADC I/F DBSC3 JTAG SDRAM Speed-pulse I/F (12 ch) DARC TCON Crypto Engine (1 ch) IR Receiver Figure 1.1 RZ/G1E System Configuration R01UH0544EJ0100 Rev.1.00 Sep 30,2016...

  • Page 10: List Of Specifications

    RZ/G1E 1. Overview List of Specifications 1.3.1 ARM Core Item Description  ARM Cortex-A7 Dual MPCore 1.0 GHz System CPU Cortex-A7  L1 I/D cache 32/32 KBytes, L2 cache 512 KBytes  NEON™/VFPv4 supported  Security extension supported ARM debugger (CoreSight™) ...

  • Page 11: Cpu Core Peripherals

     Setting multiplexed pin functions for LSI pins Pin function controller (PFC) Function of the RZ/G1E pin selectable by setting the registers in the PFC module  Module selection Enable and disable the functions of RZ/G1E LSI pins to which pin functions from multiple pin groups are assigned by setting the registers in the PFC module.

  • Page 12: External Bus Module

    RZ/G1E 1. Overview 1.3.3 External Bus Module Item Description  EX-BUS interface: max. 16-bit bus Local bus state controller  Frequency: 65 MHz (LBSC)  External area divided into several areas and managed  Allocation to space of area 0, area 1, and area 6 or allocation to space of area 0 only is selected at startup time.
  • Page 13 RZ/G1E 1. Overview Item Description  Number of channels: LBSC-DMAC three channels LBSC-DMAC  Address space: Physical address space  Transfer direction: Peripheral to memory (AXI-bus), memory (AXI-bus) to peripheral  Data packing for peripheral read data: Memory write data length is selectable as transfer data length to memory side.

  • Page 14: Internal Bus Module

    RZ/G1E 1. Overview 1.3.4 Internal Bus Module Item Description  On-chip main bus AXI-bus  Bus protocol : AXI3 with QoS control  Frequency: 260 MHz  Bus width: 256 bits/128 bits  On-chip CPU & GPU main bus  Corelink™ CCI-400 Cache Coherent Interconnect - r0p3 ...

  • Page 15: Local Memory

    RZ/G1E 1. Overview Item Description Direct memory access Audio-DMAC (for transfer from Peripheral to Peripheral) controller  29 channels for audio domain (Audio-DMAC-  Data transfer length: longword (4 Bytes) Peripheral-Peripheral)  Transfer count: Transfer count is not specified (DMA transfer is made from the transfer-start to transfer-stop settings.)

  • Page 16: Graphics Units

    RZ/G1E 1. Overview 1.3.6 Graphics Units Item Description  Imagination Technologies PowerVR Series5 SGX540 (260 MHz) 3D graphics engine (3DGE)  USSE2 delivers twice the peak floating point and instruction throughput of Series5 USSE  YCbCr and color space accelerators for improved performance ...
  • Page 17 RZ/G1E 1. Overview Item Description  Video input (VIN) Input data format 8-, 10-, or 12-bit YCbCr422 (CbYCrY format)  16-bit YCbCr422 (8 bits (Y) + 8 bits (CbCr) format)  20-bit YCbCr422 (10 bits (Y) + 10 bits (CbCr) format) ...

  • Page 18: Video Processing

    1.3.7 Video Processing Item Description Video signal processor 1 The VSP1 is the successor IP of Renesas’ VIO6-IP series, and has the following (VSP1) features. (1) Supports Various Data Formats and Conversion  Supports YCbCr444/422/420, RGB, αRGB, αplane  Color space conversion and changes to the number of colors by dithering ...
  • Page 19 RZ/G1E 1. Overview Item Description Video processing unit The VCP3 is a multi-codec module which provides encoding and decoding capabilities on the basis of multiple video coding schemes, e.g., H.264/AVC, MPEG-4, MPEG-2 and (VCP3) VC-1. This IP (Intellectual Property) is a multi codec that processes the frame or each field by controlling software for VCP3 executed on host CPU.
  • Page 20 RZ/G1E 1. Overview Item Description  Supports conversion between various RGB formats. 2-dimensional DMAC (2D-DMAC)  Image extraction function: Capable of extracting an image and storing it as a separate image in the RAM.  Image rotation/reversal function: Reverses an image vertically/horizontally or rotates it by 90°/270°.

  • Page 21: Sound Interface

    RZ/G1E 1. Overview 1.3.8 Sound Interface Item Description  Includes six SRC modules Sampling rate converter Overall unit (SCU) specification  Supports the quality suitable for audio sound (THD+N -132dB) : four modules  Supports the quality suitable for voice sound (THD+N -96dB) : two modules ...
  • Page 22 RZ/G1E 1. Overview Item Description  Serial sound interface unit Overall Includes ten SSI modules functioning as interfaces with external (SSIU) specification devices.  Supports short and long formats  Supports TDM format (six modules of ten modules can be used for this function) ...

  • Page 23: Storage

    RZ/G1E 1. Overview 1.3.9 Storage Item Description  2 channels (Host only 1 channel/Host-Function 1 channel) USB2.0 host & function module  PHY integrated (USB2.0)  USB Host (EHCI/OHCI) 2LINK  Compliance with USB2.0  USB Function 1LINK  Compliance with USB2.0 (High-Speed) ...

  • Page 24: Network

    RZ/G1E 1. Overview 1.3.10 Network Item Description  2 channels CAN interface (CAN)  Supports CAN specification 2.0B  ISO-11898-1 compliant  Maximum bit rate: 1 Mbps  Message box  Normal mode: 32 receive-only mailboxes and 32 mailboxes for transmission/reception ...
  • Page 25 RZ/G1E 1. Overview Item Description  Two channels Compare match timer 0 (CMT0)  32-bit timer (16 bits/32 bits can be selected)  Source clock: RCLK clock  Compare match function provided  Interrupt requests  Eight channels Compare match timer 1 (CMT1) ...

  • Page 26: Peripheral Module

    RZ/G1E 1. Overview 1.3.12 Peripheral Module Item Description  1 channel for 3.3 V LVTTL buffers and 1 channel for open drain type IO buffer I2C bus interface (IIC)  Supports single master transmission/reception  Interrupt request  DMAC request Multi-master I2C bus ...
  • Page 27 RZ/G1E 1. Overview Item Description  6 channels Serial communication Overall interface with FIFO specification  Asynchronous, clock-synchronized modes (SCIF)  Asynchronous serial communication mode The SCIF performs serial data communication based on a character-by- character asynchronous system. This feature enables serial data...
  • Page 28 RZ/G1E 1. Overview Item Description  3 channels Clock-synchronized serial interface with  Max. speed: 26 Mbps FIFO (MSIOF)  Internal 64-Byte transmit FIFOs/internal 256-Byte receive FIFOs  Supports master and slave modes  Internal prescaler  Supports serial formats: IIS, SPI (master and slave modes) ...

  • Page 29: Others

    RZ/G1E 1. Overview 1.3.13 Others Item Description JTAG JTAG interface for CoreSight Process 28nm Si-CMOS Package FC-BGA2121-501 Power Supply Voltages and Temperature Range • Power supply voltage (typ.) 1.8 V: (ETM, SD, LVCMOS I/F, Xtal, JTAG, Trace and RST) 1.03 V: (core) 1.5 V: (DDR3-I/O SSTL Mode:DDR3)

  • Page 30: Area Map

    RZ/G1E 2. Area Map 2. Area Map See section 2, Area Map in the RZ/G Series User’s Manual: Hardware. R01UH0544EJ0100 Rev.1.00 Sep 30,2016...

  • Page 31: Pin Assignment

    RZ/G1E 3. Pin Assignment 3. Pin Assignment Top View (Left) M0A12 M0A6 M0A10 M0A11 M0BA1 M0A2 M0A15 PRESET CLKOUT EX_CS5# M0A13 M0A5 M0A0 M0A3 M0A9 M0A1 M0A4 OUT# VDDQ_M0BK EX_CS4# EX_WAIT0 VDDQ_M0 M0CK1# M0CK1 VDDQ_M0 EX_CS2# EX_CS3# M0A14 M0A8 M0ZQ...

  • Page 32: Top View (Right)

    RZ/G1E 3. Pin Assignment Top View (Right) M0CK0# M0CK0 M0DQS1# M0DQS1 M0DQS0# M0DQS0 M0DQ6 M0DQ2 M0A7 VDDQ_M0 M0ODT0 M0DQ8 M0DQ14 M0DQ10 M0DQ11 VDDQ_M0 M0DQ3 M0DQ5 M0DQ22 M0VREFDQ0 M0CS0# VDDQ_M0 VDDQ_M0 M0DQ4 M0DM0 M0DQ7 M0DQ23 M0DQ19 M0VREFCA M0CKE0 M0RAS# M0DQ9 M0DM1...

  • Page 33: Mode Pin Settings

    RZ/G1E 3. Pin Assignment Mode Pin Settings Input fixed values for BSMODE pins. These values cannot be changed after power is supplied. The values of pins MD0 to MD14, MD18 to MD21, MDT0 and MDT1 are input upon power-on reset using the PRESET pin. Power-on reset results in switching to a different function.
  • Page 34 RZ/G1E 3. Pin Assignment MD21, MD12 MD10 MD20 MD11 [1:0] JTAG SDHI1 — — Boundary SCAN Normal mode Normal mode — — Reserved Reserved Reserved — Coresight debug port Normal mode Normal mode Reserved Normal mode Reserved Normal mode Normal mode...

  • Page 35: Pin Multiplexing

    4. Pin Multiplexing List of Multiplexed Pin Functions Table 4.1 lists the multiplexed pin functions of the RZ/G1E. The default pin function of each pin after power-on reset is "Function 1" respectively, unless otherwise mentioned. For details on pin function control, refer to section 3.3, Mode Pin Settings and section 5, Pin Function Controller (PFC).
  • Page 36 RZ/G1E 4. Pin Multiplexing Table 4.1 List of Multiplexed Pin Functions DBSC3 (No.1 to 40): Single Function Function 1 Function 1 Module During POR Module During POR Pin No. Pin Name V(power)/|IOH| Pin No. Pin Name V(power)/|IOH| Pull-up Pull-up DBSC3...
  • Page 37 RZ/G1E 4. Pin Multiplexing DBSC3 (No.41 to 80): Single Function Function 1 Function 1 Module During POR Module During POR Pin No. Pin Name V(power)/|IOH| Pin No. Pin Name V(power)/|IOH| Pull-up Pull-up DBSC3 DBSC3 M0DQ2 1.5/1.35V(VDDQ_M0)/- M0DQS1 1.5/1.35V(VDDQ_M0)/- IO(Z) IO(Z*)
  • Page 38 RZ/G1E 4. Pin Multiplexing DBSC3 (No.81 to 93): Single Function Function 1 Module During POR Pin No. Pin Name V(power)/|IOH| Pull-up DBSC3 M0DQ25 1.5/1.35V(VDDQ_M0)/- IO(Z) DBSC3 M0DQ26 1.5/1.35V(VDDQ_M0)/- IO(Z) DBSC3 M0DQ27 1.5/1.35V(VDDQ_M0)/- IO(Z) DBSC3 M0DQ28 1.5/1.35V(VDDQ_M0)/- IO(Z) DBSC3 M0DQ29 1.5/1.35V(VDDQ_M0)/-...
  • Page 39 RZ/G1E 4. Pin Multiplexing CPG, RESET, SYSTEM, Debug, USB (No.94 to 116): Single Function Function 1 Function 1 Module During POR Module During POR Pin No. Pin Name V(power)/|IOH| Pin No. Pin Name V(power)/|IOH| Pull-up Pull-up Debug EXTAL 1.8V(VCCQ18)/- 1.8V(VCCQ18)/-...
  • Page 40 RZ/G1E 4. Pin Multiplexing USB 2.0, INTC, SDHI and GPIO (No.117 to 136): Up to 2-Function Multiplexed Following pins multiplexed with the GPIO are set for GPIO function after power-on reset except for USB pins. For details, refer to GPSR5 and GPSR6 registers in section 5, Pin Function Controller (PFC).
  • Page 41 RZ/G1E 4. Pin Multiplexing SDHI, INTC, RCAN, MMC, SCIF, I2C and GPIO (No.137 to 156): Up to 5-Function Multiplexed Pin states during POR and default pin function (GPIO or DBG: debugging mode) after power-on reset depend on mode pins setting except for No.145 and 156. For details, refer to Mode Pin Settings in section 3.3, GPSR6 register in section 5, Pin Function Controller (PFC) and section 62, CoreSight for DBG.
  • Page 42 RZ/G1E 4. Pin Multiplexing LBSC, SCIFA, INTC, I2C, SCIF, TMU, PWM, HSCIF, SCIFB and GPIO (No.157 to 176): Up to 6-Function Multiplexed and Mode Pin assigned (No.173 to 176) Default pin function (function 1 or GPIO) after power-on reset is defined by MD[3:1] pins setting.
  • Page 43 RZ/G1E 4. Pin Multiplexing LBSC, SCIFB, PWM, TPU, SCIFA, MSIOF, IIC, HSCIF, RCAN, QSPI and GPIO (No.177 to 196): Up to 8- Function Multiplexed and Mode Pin assigned (No.177, 180, 182, 186, 188, 191 and 192) Default pin function (function 1 or GPIO) after power-on reset is defined by MD[3:1] pins setting.
  • Page 44 RZ/G1E 4. Pin Multiplexing LBSC, QSPI, VIN, TPU, SCIFB, PWM, SCIF, SCIFA, I2C, RCAN and GPIO (No.197 to 215): Up to 9-Function Multiplexed and Mode Pin assigned (No.208 to 212 and 215) Default pin function (function 1 or GPIO) after power-on reset is defined by MD[3:1] pins setting except for No.199, 202 to 207, 210, 214 and 215.
  • Page 45 RZ/G1E 4. Pin Multiplexing DU, SCIF, I2C, SCIFA, RCAN and GPIO (No.216 to 235): Up to 6-Function Multiplexed These pins are set for GPIO after power-on reset. For details, refer to GPSR2 register in section 5, Pin Function Controller (PFC).
  • Page 46 RZ/G1E 4. Pin Multiplexing DU, VIN, EtherAVB and GPIO (No.236 to 256): Up to 3-Function Multiplexed and Mode Pin assigned (No.243, 244, 246 and 247) These pins are set for GPIO after power-on reset. For details, refer to GPSR2 and GPSR3 registers in section 5, Pin Function Controller (PFC).
  • Page 47 RZ/G1E 4. Pin Multiplexing VIN, I2C, SCIFA, EthernetAVB, ADG, EtherMAC, MSIOF, RCAN, SCIF, IIC, SSI, HSCIF and GPIO (No.257 to 277): Up to 8-Function Multiplexed These pins are set for GPIO after power-on reset. For details, refer to GPSR3 register in section 5, Pin Function Controller (PFC).
  • Page 48 RZ/G1E 4. Pin Multiplexing I2C, SCIF, PWM, TMU, EthernetAVB, RCAN, TPU, SCU, DU, INTC, MSIOF, SCIFA, HSCIF, SSI, IIC and GPIO (No.278 to 298): Up to 9-Function Multiplexed These pins are set for GPIO after power-on reset. For details, refer to GPSR3 and GPSR4 registers in section 5, Pin Function Controller (PFC).
  • Page 49 RZ/G1E 4. Pin Multiplexing SCIF, INTC, DU, SSI, I2C, ADG, SCIFA, RCAN, MSIOF, PWM, LBSC and GPIO (No.299 to 318): Up to 9- Function Multiplexed These pins are set for GPIO after power-on reset. For details, refer to GPSR4 and GPSR5 registers in section 5, Pin Function Controller (PFC).
  • Page 50 RZ/G1E 4. Pin Multiplexing SSI, SCIF, PWM, INTC, LBSC, EtherMAC, IIC, VIN, RCAN, HSCIF, SCIFA, I2C and GPIO (No.319 to 334): Up to 9-Function Multiplexed These pins are set for GPIO after power-on reset except for No.322 to 324. For details, refer to GPSR5 register in section 5, Pin Function Controller (PFC).
  • Page 51 RZ/G1E 4. Pin Multiplexing ADG, I2C, SCIFA, VIN, EtherMAC, IIC and GPIO (No.335 to 340): Up to 9-Function Multiplexed These pins are set for GPIO after power-on reset except for No.339 and 340. For details, refer to GPSR5 register in section 5, Pin Function Controller (PFC).

  • Page 52: Pin States

    RZ/G1E 4. Pin Multiplexing Pin States Table 4.2 is pin state of the RZ/G1E. [Legend] No.: Serial number, Pin No.: BGA package ball grid number, Pin Name: Pin name of function 1 in pin in Table 4.1, I/O: Input or output direction of the pin name column pin (function 1).
  • Page 53 RZ/G1E 4. Pin Multiplexing Table 4.2 Pin States During Default Default Pin No. Pin Name (Function 1) Default Pin Function State Pull-up M0CKE0 M0CKE0 O(L) M0CKE1 M0CKE1 O(L) M0VREFCA M0BKPRST# M0BKPRST# M0RESET# M0RESET# H to L M0CK0 M0CK0 M0CK0# M0CK0#...
  • Page 54 RZ/G1E 4. Pin Multiplexing During Default Default Pin No. Pin Name (Function 1) Default Pin Function State Pull-up M0DM0 M0DM0 VDDQ_M0DPLL0 VSSQ_M0DPLL0 M0VREFDQ0 M0DQ8 M0DQ8 M0DQ9 M0DQ9 M0DQ10 M0DQ10 M0DQ11 M0DQ11 M0DQ12 M0DQ12 M0DQ13 M0DQ13 M0DQ14 M0DQ14 M0DQ15 M0DQ15 M0DQS1...
  • Page 55 RZ/G1E 4. Pin Multiplexing During Default Default Pin No. Pin Name (Function 1) Default Pin Function State Pull-up K16/L16 VSS_CPGPLL1 K12/L12 VDD_CPGPLL3 K11/L11 VSS_CPGPLL3 PRESET# I(L) PRESET# PRESETOUT# PRESETOUT# L to H BSMODE BSMODE TRST# I(L) TRST# On(pulldown) USB_EXTAL USB_EXTAL...
  • Page 56 RZ/G1E 4. Pin Multiplexing During Default Default Pin No. Pin Name (Function 1) Default Pin Function State Pull-up AA11 MMC_D1 GP6_19/TMS3(* Off/-(* MMC_D2 GP6_20/TDI3(* Off/-(* AA10 MMC_D3 GP6_21(* Off/-(* AB10 MMC_D4 GP6_22 AD10 MMC_D5 GP6_23 MMC_D6 GP6_24 AB11 MMC_D7 GP6_25...
  • Page 57 RZ/G1E 4. Pin Multiplexing During Default Default Pin No. Pin Name (Function 1) Default Pin Function State Pull-up CLKOUT CLKOUT CS0# CS0#/GP1_10(* CS1#/A26 [CS1#/A26]/GP1_11 [H/L] (* EX_CS0# GP1_12 EX_CS1# GP1_13 EX_CS2# GP1_14 EX_CS3# GP1_15 EX_CS4# GP1_16 EX_CS5# GP1_17 I(MD8) BS#/GP1_18(*...
  • Page 58 RZ/G1E 4. Pin Multiplexing During Default Default Pin No. Pin Name (Function 1) Default Pin Function State Pull-up VI0_DATA0/VI0_B0 GP3_1 VI0_DATA1/VI0_B1 GP3_2 VI0_DATA2/VI0_B2 GP3_3 VI0_DATA3/VI0_B3 GP3_4 VI0_DATA4/VI0_B4 GP3_5 VI0_DATA5/VI0_B5 GP3_6 VI0_DATA6/VI0_B6 GP3_7 VI0_DATA7/VI0_B7 GP3_8 VI0_CLKENB GP3_9 VI0_FIELD GP3_10 VI0_HSYNC# GP3_11...
  • Page 59 RZ/G1E 4. Pin Multiplexing During Default Default Pin No. Pin Name (Function 1) Default Pin Function State Pull-up AA22 SCIF3_SCK GP4_19 AC22 SCIF3_RXD GP4_20 AC21 SCIF3_TXD GP4_21 AD21 I2C2_SCL GP4_22 AC20 I2C2_SDA GP4_23 AE22 SSI_SCK5 GP4_24 AB20 SSI_WS5 GP4_25 AA20...
  • Page 60 RZ/G1E 4. Pin Multiplexing 4. No.157 to 198, 200, 201, 208, 209, and 211 to 213 Default pin function: MD[3:1] = 000: LBSC (D[15:0], A[25:0], CS0#, CS1#/A26, BS#, RD#, WE[1:0]#, and EX_WAIT0) MD[3:1] ≠ 000: GPIO (GP0_[31:0], GP1_[11:0], [19:18], [23:21]) 5.

  • Page 61: Handling Of Unused Pins

    4. Pin Multiplexing Handling of Unused Pins Table 4.3 shows a handling of unused pins of the RZ/G1E. "Unused pin" means all modules that are multiplexed to the pin should be disable and unused in this section. For handling of some unused pin which belongs to the enable module should be handled following the notification of the module manual.
  • Page 62 RZ/G1E 4. Pin Multiplexing Table 4.3 Handling of Unused Pins Default Mode Default Pin No. Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use M0CKE0 O(L) Open M0CKE1 O(L) Open M0VREFCA Must be used M0BKPRST# Pulled-up to VDDQ_M0BKUP or pulled-down to VSS...
  • Page 63 RZ/G1E 4. Pin Multiplexing Default Mode Default Pin No. Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use M0DM0 Open VDDQ_M0DPLL0 Must be used VSSQ_M0DPLL0 Must be used M0VREFDQ0 Must be used M0DQ8 Open M0DQ9 Open...
  • Page 64 RZ/G1E 4. Pin Multiplexing Default Mode Default Pin No. Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use K16/L16 VSS_CPGPLL1 Must be used K12/L12 VDD_CPGPLL3 Must be used K11/L11 VSS_CPGPLL3 Must be used PRESET# Must be used...
  • Page 65 RZ/G1E 4. Pin Multiplexing Default Mode Default Pin No. Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use MMC_D0 Off/-(* Pulled-up to VCCQ_MMC_SD2 or pulled-down to VSS AA11 MMC_D1 Off/-(* Pulled-up to VCCQ_MMC_SD2 or pulled-down to VSS...
  • Page 66 RZ/G1E 4. Pin Multiplexing Default Mode Default Pin No. Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use QSPI Open CLKOUT Open Area 0 CS0# Open Area 0 [H or L] [CS1#/A26] Open Area 0 EX_CS0#...
  • Page 67 RZ/G1E 4. Pin Multiplexing Default Mode Default Pin No. Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use AC13 DU0_EXODDF/DU0_O Open DDF/DISP/CDE AE18 DU0_DISP Pulled-up to VCCQ or pulled-down to VSS MD10 - AB13 DU0_CDE Pulled-up to VCCQ or pulled-down to VSS...
  • Page 68 RZ/G1E 4. Pin Multiplexing Default Mode Default Pin No. Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use AD25 SCIF1_RXD Open AC24 SCIF1_TXD Open AD23 SCIF2_RXD Open AE23 SCIF2_TXD Open AE24 SCIF2_SCK Open AA22 SCIF3_SCK Open...
  • Page 69 RZ/G1E 4. Pin Multiplexing Notes: 1. No.47, 48, 61, 62, 74, 75, 88 and 89 (M0DQSx and M0DQSx#) pin states during POR and default state: The drivers output states are both high-impedance (Z), and the internal circuit controls pin levels as low-level for the M0DQSx pin and high-level for the M0DQSx# pin respectively.

  • Page 70: Pin Function Controller (Pfc)

    • Module selection Enable and disable the functions of RZ/G1E LSI pins to which pin functions from multiple pin groups are assigned by setting the registers in the PFC module. (Selection is handled by the module select register (MOD_SEL), module select register 2 (MOD_SEL2), and module select register 3 (MOD_SEL3).

  • Page 71: Register Configuration

    RZ/G1E 5. Pin Function Controller (PFC) Register Configuration All the registers in the PFC are mapped into the APB bus space. Table 5.1 shows the configuration of the registers provided in the PFC. Details on each register in the PFC are given in sections 5.2.1 to 5.3.48.
  • Page 72 RZ/G1E 5. Pin Function Controller (PFC) Access Name Abbr. Initial Value Address Size Condition Peripheral function select IPSR10 H'0000 0000 H'E606 0048 — register 10 Peripheral function select IPSR11 H'0000 0000 H'E606 004C — register 11 Peripheral function select IPSR12...

  • Page 73: Register Description

    RZ/G1E 5. Pin Function Controller (PFC) Register Description [Legend] Initial value: Register value after a reset — : Undefined value R/W: Readable/writable. The written value can be read. Read-only. The write value should always be 0. R/WC0: Readable/writable. Writing 0 initializes the bit. Writing 1 is ignored.

  • Page 74: Lsi Multiplexed Pin Setting Mask Register (Pmmr)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.1 LSI Multiplexed Pin Setting Mask Register (PMMR) Function: PMMR enables/disables writing to the multiplexed pin setting registers. Bit: PMMR Initial value: R/W: Bit: PMMR Initial value: R/W: Note: This register must be set before setting each of the GPIO/peripheral function select registers GPSR0 to GPSR6, peripheral function select registers IPSR0 to IPSR13, module select registers MOD_SEL, MOD_SEL2 and MOD_SEL3, IO cell control registers IOCTRL0 to IOCTRL3 and IOCTRL7.
  • Page 75 RZ/G1E 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP0[0] GP-0-0 peripheral function selected by IP0[23:22] GP0[1] GP-0-1 peripheral function selected by IP0[24] GP0[2] GP-0-2 peripheral function selected by IP0[25]...

  • Page 76: Gpio/Peripheral Function Select Register 1 (Gpsr1)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.3 GPIO/Peripheral Function Select Register 1 (GPSR1) Function: GPSR1 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 77 RZ/G1E 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP1[22] GP-1-22 WE1_N GP1[23] GP-1-23 Peripheral function selected by IP4[1:0] GP1[24] GP-1-24 Peripheral function selected by IP7[31] GP1[25] GP-1-25 DACK0 GP1[26]...

  • Page 78: Gpio/Peripheral Function Select Register 2 (Gpsr2)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.4 GPIO/Peripheral Function Select Register 2 (GPSR2) Function: GPSR2 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 79 RZ/G1E 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP2[25] GP-2-25 Peripheral function selected by IP5[27:26] GP2[26] GP-2-26 Peripheral function selected by IP5[29:28] GP2[27] GP-2-27 Peripheral function selected by IP5[31:30]...

  • Page 80: Gpio/Peripheral Function Select Register 3 (Gpsr3)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.5 GPIO/Peripheral Function Select Register 3 (GPSR3) Function: GPSR3 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 81 RZ/G1E 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP3[25] GP-3-25 Peripheral function selected by IP8[5:3] GP3[26] GP-3-26 Peripheral function selected by IP8[8:6] GP3[27] GP-3-27 Peripheral function selected by IP8[11:9]...

  • Page 82: Gpio/Peripheral Function Select Register 4 (Gpsr4)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.6 GPIO/Peripheral Function Select Register 4 (GPSR4) Function: GPSR4 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 83 RZ/G1E 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP4[25] GP-4-25 Peripheral function selected by IP11[2:0] GP4[26] GP-4-26 Peripheral function selected by IP11[5:3] GP4[27] GP-4-27 Peripheral function selected by IP11[7:6]...

  • Page 84: Gpio/Peripheral Function Select Register 5 (Gpsr5)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.7 GPIO/Peripheral Function Select Register 5 (GPSR5) Function: GPSR5 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 85 RZ/G1E 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP5[25] GP-5-25 USB0_OVC GP5[26] GP-5-26 USB1_PWEN GP5[27] GP-5-27 USB1_OVC GP5[28] GP5[29] GP5[30] GP5[31] R01UH0544EJ0100 Rev.1.00 5-16 Sep 30,2016...

  • Page 86: Gpio/Peripheral Function Select Register 6 (Gpsr6)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.8 GPIO/Peripheral Function Select Register 6 (GPSR6) Function: GPSR6 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 87 RZ/G1E 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP6[25] GP-6-25 Peripheral function selected by IP0[21:20] GP6[26] GP6[27] GP6[28] GP6[29] GP6[30] GP6[31] R01UH0544EJ0100 Rev.1.00 5-18 Sep 30,2016...

  • Page 88: Peripheral Function Select Register 0 (Ipsr0)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.9 Peripheral Function Select Register 0 (IPSR0) Function: IPSR0 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 89: Peripheral Function Select Register 1 (Ipsr1)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.10 Peripheral Function Select Register 1 (IPSR1) Function: IPSR1 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 90: Peripheral Function Select Register 2 (Ipsr2)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.11 Peripheral Function Select Register 2 (IPSR2) Function: IPSR2 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 91: Peripheral Function Select Register 3 (Ipsr3)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.12 Peripheral Function Select Register 3 (IPSR3) Function: IPSR3 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 92: Peripheral Function Select Register 4 (Ipsr4)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.13 Peripheral Function Select Register 4 (IPSR4) Function: IPSR4 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 93: Peripheral Function Select Register 5 (Ipsr5)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.14 Peripheral Function Select Register 5 (IPSR5) Function: IPSR5 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 94: Peripheral Function Select Register 6 (Ipsr6)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.15 Peripheral Function Select Register 6 (IPSR6) Function: IPSR6 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 95: Peripheral Function Select Register 7 (Ipsr7)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.16 Peripheral Function Select Register 7 (IPSR7) Function: IPSR7 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 96: Peripheral Function Select Register 8 (Ipsr8)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.17 Peripheral Function Select Register 8 (IPSR8) Function: IPSR8 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 97: Peripheral Function Select Register 9 (Ipsr9)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.18 Peripheral Function Select Register 9 (IPSR9) Function: IPSR9 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 98: Peripheral Function Select Register 10 (Ipsr10)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.19 Peripheral Function Select Register 10 (IPSR10) Function: IPSR10 selects the functions of the multiplexed LSI pins. Bit: IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10...

  • Page 99: Peripheral Function Select Register 11 (Ipsr11)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.20 Peripheral Function Select Register 11 (IPSR11) Function: IPSR11 selects the functions of the multiplexed LSI pins. Bit: IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11...

  • Page 100: Peripheral Function Select Register 12 (Ipsr12)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.21 Peripheral Function Select Register 12 (IPSR12) Function: IPSR12 selects the functions of the multiplexed LSI pins. Bit: IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12...

  • Page 101: Peripheral Function Select Register 13 (Ipsr13)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.22 Peripheral Function Select Register 13 (IPSR13) Function: IPSR13 selects the functions of the multiplexed LSI pins. Bit: IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13...
  • Page 102 RZ/G1E 5. Pin Function Controller (PFC) Table 5.2 shows the correspondence between the function signals and the bit settings in the GPIO/peripheral function select registers and peripheral function selecting registers. Table 5.2 Correspondence between Function Signals and Register Bit Settings...
  • Page 103 RZ/G1E 5. Pin Function Controller (PFC) Peripheral-Module-(GP-Set-Value-=-1) GPIO/ Function-Selected-by-IP-Bits GPIO Peripheral Peripheral- (GP-Set- Function-1 Function-2 Function-3 Function-4 Function-5 Function-6 Function-7 Function-8 -Function- Function- Value-=- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- Selecting- Selecting- Value-=-0) Value-=-1) Value-=-2) Value-=-3) Value-=-4) Value-=-5)
  • Page 104 RZ/G1E 5. Pin Function Controller (PFC) Peripheral-Module-(GP-Set-Value-=-1) GPIO/ Function-Selected-by-IP-Bits GPIO Peripheral Peripheral- (GP-Set- Function-1 Function-2 Function-3 Function-4 Function-5 Function-6 Function-7 Function-8 -Function- Function- Value-=- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- Selecting- Selecting- Value-=-0) Value-=-1) Value-=-2) Value-=-3) Value-=-4) Value-=-5)
  • Page 105 RZ/G1E 5. Pin Function Controller (PFC) Peripheral-Module-(GP-Set-Value-=-1) GPIO/ Function-Selected-by-IP-Bits GPIO Peripheral Peripheral- (GP-Set- Function-1 Function-2 Function-3 Function-4 Function-5 Function-6 Function-7 Function-8 -Function- Function- Value-=- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- Selecting- Selecting- Value-=-0) Value-=-1) Value-=-2) Value-=-3) Value-=-4) Value-=-5)
  • Page 106 RZ/G1E 5. Pin Function Controller (PFC) Peripheral-Module-(GP-Set-Value-=-1) GPIO/ Function-Selected-by-IP-Bits GPIO Peripheral Peripheral- (GP-Set- Function-1 Function-2 Function-3 Function-4 Function-5 Function-6 Function-7 Function-8 -Function- Function- Value-=- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- Selecting- Selecting- Value-=-0) Value-=-1) Value-=-2) Value-=-3) Value-=-4) Value-=-5)
  • Page 107 RZ/G1E 5. Pin Function Controller (PFC) Peripheral-Module-(GP-Set-Value-=-1) GPIO/ Function-Selected-by-IP-Bits GPIO Peripheral Peripheral- (GP-Set- Function-1 Function-2 Function-3 Function-4 Function-5 Function-6 Function-7 Function-8 -Function- Function- Value-=- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- (IP-Set- Selecting- Selecting- Value-=-0) Value-=-1) Value-=-2) Value-=-3) Value-=-4) Value-=-5)

  • Page 108: Module Select Register (Mod_Sel)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.23 Module Select Register (MOD_SEL) Function: MOD_SEL selects the group for multiple LSI pins with multiplexed pin functions. Each input or input/output signal of the ADG, ADI, CAN, DR, I2C and AVB an is assigned to two or more groups of pins.
  • Page 109 RZ/G1E 5. Pin Function Controller (PFC) Function 1 Function 2 Function 3 Function 4 Function 5 Bit Name (Set Value = H'0) (Set Value = H'1) (Set Value = H'2) (Set Value = H'3) (Set Value = H'4) sel_eth[0] + select pin ETH_CRS_DV for...

  • Page 110: Module Select Register 2 (Mod_Sel2)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.24 Module Select Register 2 (MOD_SEL2) Function: MOD_SEL2 selects the group for multiple LSI pins with multiplexed pin functions. Each input or input/output signal of the IIC, LBS, MSI, RAD, SCIF, TMU, CAN and HSCIF is assigned to two or more groups of pins.
  • Page 111 RZ/G1E 5. Pin Function Controller (PFC) Function 1 Function 2 Function 3 Function 4 Function 5 Bit Name (Set Value = H'0) (Set Value = H'1) (Set Value = H'2) (Set Value = H'3) (Set Value = H'4) sel_msi2[0] + select pin A14 for function...
  • Page 112 RZ/G1E 5. Pin Function Controller (PFC) Function 1 Function 2 Function 3 Function 4 Function 5 Bit Name (Set Value = H'0) (Set Value = H'1) (Set Value = H'2) (Set Value = H'3) (Set Value = H'4) sel_hscif1[0] + select pin HSCIF1_HCTS_N...

  • Page 113: Module Select Register 3 (Mod_Sel3)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.25 Module Select Register 3 (MOD_SEL3) Function: MOD_SEL3 selects the group for multiple LSI pins with multiplexed pin functions. Each input or input/output signal of the SCIF and SSI is assigned to two or more groups of pins. Select one of these groups when using these signals.
  • Page 114 RZ/G1E 5. Pin Function Controller (PFC) Function 1 Function 2 Function 3 Function 4 Function 5 Bit Name (Set Value = H'0) (Set Value = H'1) (Set Value = H'2) (Set Value = H'3) (Set Value = H'4) sel_scif5[1:0] + select pin MSIOF0_RXD for...

  • Page 115: Lsi Pin Pull-Up Control Register 0 (Pupr0)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.26 LSI Pin Pull-Up Control Register 0 (PUPR0) Function: PUPR0 performs on/off control of the pull-up resistors. Bit: PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0 PUPR0...
  • Page 116 RZ/G1E 5. Pin Function Controller (PFC) Bit Name Set Value = 1 PUPR0[6] D6 is pull up PUPR0[5] D5 is pull up PUPR0[4] D4 is pull up PUPR0[3] D3 is pull up PUPR0[2] D2 is pull up PUPR0[1] D1 is pull up...

  • Page 117: Lsi Pin Pull-Up Control Register 1 (Pupr1)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.27 LSI Pin Pull-Up Control Register 1 (PUPR1) Function: PUPR1 performs on/off control of the pull-up resistors. Bit: PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1 PUPR1...
  • Page 118 RZ/G1E 5. Pin Function Controller (PFC) Bit Name Set Value = 1 PUPR1[6] A22 is pull up PUPR1[5] A21 is pull up PUPR1[4] A20 is pull up PUPR1[3] A19 is pull up PUPR1[2] A18 is pull up PUPR1[1] A17 is pull up...

  • Page 119: Lsi Pin Pull-Up Control Register 2 (Pupr2)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.28 LSI Pin Pull-Up Control Register 2 (PUPR2) Function: PUPR2 performs on/off control of the pull-up resistors. Bit: PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2 PUPR2...
  • Page 120 RZ/G1E 5. Pin Function Controller (PFC) Bit Name Set Value = 1 PUPR2[6] DU0_DR6 is pull up PUPR2[5] DU0_DR5 is pull up PUPR2[4] DU0_DR4 is pull up PUPR2[3] DU0_DR3 is pull up PUPR2[2] DU0_DR2 is pull up PUPR2[1] DU0_DR1 is pull up...

  • Page 121: Lsi Pin Pull-Up Control Register 3 (Pupr3)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.29 LSI Pin Pull-Up Control Register 3 (PUPR3) Function: PUPR3 performs on/off control of the pull-up resistors. Bit: PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3 PUPR3...
  • Page 122 RZ/G1E 5. Pin Function Controller (PFC) Bit Name Set Value = 1 PUPR3[6] VI0_DATA7_VI0_B7 is pull up PUPR3[5] VI0_DATA6_VI0_B6 is pull up PUPR3[4] VI0_DATA5_VI0_B5 is pull up PUPR3[3] VI0_DATA4_VI0_B4 is pull up PUPR3[2] VI0_DATA3_VI0_B3 is pull up PUPR3[1] VI0_DATA2_VI0_B2 is pull up...

  • Page 123: Lsi Pin Pull-Up Control Register 4 (Pupr4)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.30 LSI Pin Pull-Up Control Register 4 (PUPR4) Function: PUPR4 performs on/off control of the pull-up resistors. Bit: PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4 PUPR4...
  • Page 124 RZ/G1E 5. Pin Function Controller (PFC) Bit Name Set Value = 1 PUPR4[6] HSCIF1_HRX is pull up PUPR4[5] MSIOF0_SS2 is pull up PUPR4[4] MSIOF0_SS1 is pull up PUPR4[3] MSIOF0_SYNC is pull up PUPR4[2] MSIOF0_SCK is pull up PUPR4[1] MSIOF0_TXD is pull up...

  • Page 125: Lsi Pin Pull-Up Control Register 5 (Pupr5)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.31 LSI Pin Pull-Up Control Register 5 (PUPR5) Function: PUPR5 performs on/off control of the pull-up resistors. Bit: PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5 PUPR5...
  • Page 126 RZ/G1E 5. Pin Function Controller (PFC) Bit Name Set Value = 1 PUPR5[6] PUPR5[5] PUPR5[4] SSI_SDATA3 is pull up PUPR5[3] SSI_WS34 is pull up PUPR5[2] SSI_SCK34 is pull up PUPR5[1] SSI_SDATA0 is pull up PUPR5[0] SSI_WS0129 is pull up R01UH0544EJ0100 Rev.1.00...

  • Page 127: Lsi Pin Pull-Up Control Register 6 (Pupr6)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.32 LSI Pin Pull-Up Control Register 6 (PUPR6) Function: PUPR6 performs on/off control of the pull-up resistors. Bit: PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6 PUPR6...
  • Page 128 RZ/G1E 5. Pin Function Controller (PFC) Bit Name Set Value = 1 PUPR6[6] SD0_WP is pull up PUPR6[5] SD0_CD is pull up PUPR6[4] SD0_DATA3 is pull up PUPR6[3] SD0_DATA2 is pull up PUPR6[2] SD0_DATA1 is pull up PUPR6[1] SD0_DATA0 is pull up...

  • Page 129: Sd Control Register 0 (Ioctrl0)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.33 SD Control Register 0 (IOCTRL0) Function: IOCTRL0 controls the driving abilities of pins in use for the MMC and SD0 interfaces. Bit: drv2_m drv1_m drv2_m drv1_m drv2_m drv1_m drv2_m drv1_m drv2_m drv1_m drv2_m...
  • Page 130 RZ/G1E 5. Pin Function Controller (PFC) Initial Bit Name Value Description drv2_sd0data2 SD0_DATA2 Setting. The value of these bits must be 11. drv1_sd0data2 Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately before setting this register.

  • Page 131: Sd Control Register 1 (Ioctrl1)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.34 SD Control Register 1 (IOCTRL1) Function: IOCTRL1 controls the driving abilities of pins in use for the SD0 and SD1 interfaces. Bit: drv2_sd drv1_sd drv2_sd drv1_sd drv2_sd drv1_sd drv2_sd drv1_sd drv2_sd drv1_sd drv2_sd...

  • Page 132: Tdsel Control Register (Ioctrl2)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.35 TDSEL Control Register (IOCTRL2) Function: IOCTRL2 controls the delay of clock of pins in use for the IRQ, DU and Ethernet interfaces. Bit: tdsel1_a tdsel0_a tdsel1_a tdsel0_a tdsel1_a tdsel0_a tdsel1_et tdsel0_et tdsel1_e tdsel0_e...

  • Page 133: Poc Control Register (Ioctrl3)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.36 POC Control Register (IOCTRL3) Function: IOCTRL3 controls the IO voltage of pins in use for the SD interfaces. Bit: poc_m poc_m poc_m poc_m poc_m poc_m poc_m poc_m poc_sd poc_sd poc_sd poc_sd poc_sd poc_sd...
  • Page 134 RZ/G1E 5. Pin Function Controller (PFC) Initial Bit Name Value Description 7 to 0 — All 0 — Notes: 1. Any pin belongs to the same SD channel must be set to the same IO voltage as VCCQ_(MMC)_SDn. Even though setting different voltage for each pin of the same SD channel, it is impossible to change each pin voltage from the power supply voltage of the VCCQ_(MMC)_SDn.

  • Page 135: Iicdvfs And Tdbg Io Cell Control Register (Ioctrl7)

    RZ/G1E 5. Pin Function Controller (PFC) 5.3.37 IICDVFS and TDBG IO cell control register (IOCTRL7) Function: IOCTRL7 controls the driving abilities of pins in use for the IIC and IICDVFS interfaces. This register is internal use and reserved; the value of this register should not be changed.

  • Page 136: Operation

    RZ/G1E 5. Pin Function Controller (PFC) Operation 5.4.1 Function Setting for Multiplexed Pins Setting the LSI multiplexed pin setting mask register (PMMR) is necessary before setting each of the GPIO/peripheral function select registers 0 to 6 (GPSR0 to GPSR6) and peripheral function select registers 0 to 13 (IPSR0 to IPSR13).

  • Page 137: Setting Pull-Up/Down Resistors

    RZ/G1E 5. Pin Function Controller (PFC) Procedure 1 for changing pin function from one peripheral function to another peripheral function Set the LSI multiplexed pin setting mask register Clock (CP φ ) Set the GPIO/peripheral function select register (GP) to GPIO...

  • Page 138: Main Revisions And Additions In This Edition

    Main Revisions and Additions in this Edition Minor revisions such as corrections of errors in spelling and modifications of wording are not included in the revision history. Description Rev. Page Contents Summary 1.00 — First edition issued R01UH0544EJ0100 Rev.1.00 Sep 30,2016...
  • Page 139 RZ/G1E User’s Manual: Hardware Publication Date: Rev.1.00 Sep 30, 2016 Published by: Renesas Electronics Corporation...
  • Page 140 SALES OFFICES SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. Renesas Electronics America Inc. 2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A.
  • Page 141 RZ/G1E R01UH0544EJ0100...

Table of Contents