Interrupts; Usage Notes; Notes On Register Access; Table 13.1 Wdt Interrupt Source - Renesas H8S Series Hardware Manual

13.4

Interrupts

During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.

Table 13.1 WDT Interrupt Source

Name Interrupt Source
WOVI TCNT overflow
13.5

Usage Notes

13.5.1

Notes on Register Access

The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT, TCSR, and RSTCSR
These registers must be written to by a word transfer instruction. They cannot be written to by a
byte transfer instruction.
TCNT and TCSR both have the same write address. Therefore, the relative condition shown in
figure 13.2 needs to be satisfied in order to write to TCNT or TCSR. The transfer instruction
writes the lower byte data to TCNT or TCSR according to the satisfied condition.
To write to RSTCSR, execute a word transfer instruction for address H'FF76. A byte transfer
instruction cannot write to RSTCSR.
The method of writing 0 to the WOVF bit differs from that of writing to the RSTE and RSTS bits.
To write 0 to the WOVF bit, satisfy the condition shown in figure 13.2. If satisfied, the transfer
instruction clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write to
the RSTE and RSTS bits, satisfy the condition shown in figure 13.2. If satisfied, the transfer
instruction writes the values in bits 5 and 6 of the lower byte into the RSTE and RSTS bits,
respectively, but has no effect on the WOVF bit.
Interrupt Flag
WOVF
Rev. 6.00 Mar 15, 2006 page 309 of 570
Section 13 Watchdog Timer
DTC Activation
Impossible
REJ09B0211-0600