Notes On Register Access - Renesas F-ZTAT H8 Series Hardware Manual

Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of
the reset signal generated if TCNT overflows during watchdog timer operation.
Bit 6: RSTOE Description
0 Reset signal is not output externally
1 Reset signal is output externally
Bits 5 to 0—Reserved: Read-only bits, always read as 1.
12.2.4

Notes on Register Access

The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte instructions. Figure 12.2 shows the format of data written to
TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be
contained in the lower byte of the written word. The upper byte must contain H'5A (password for
TCNT) or H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT
or TCSR.
TCNT write
Address
TCSR write
Address
Note: Lower 16 bits of the address.
*
Figure 12.2 Format of Data Written to TCNT and TCSR
15
H'FFA8*
15
H'FFA8*
8 7
H'5A
8 7
H'A5
Rev. 7.00 Sep 21, 2005 page 443 of 878
Section 12 Watchdog Timer
(Initial value)
0
Write data
0
Write data
REJ09B0259-0700