Input Sampling And A/D Conversion Time; Figure 16.2 A/D Conversion Timing - Renesas H8 Series Hardware Manual

Section 16 A/D Converter
16.4.3

Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
starts conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 shows the A/D
conversion time.
As indicated in figure 16.2, the A/D conversion time includes t
length of t varies depending on the timing of the write access to ADCSR. The total conversion
D
time therefore varies within the ranges indicated in table 16.3.
In scan mode, the values given in table 16.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states
(fixed) when CKS = 1.
Rev. 3.00 Sep. 14, 2006 Page 280 of 408
REJ09B0105-0300
(1)
φ
Address (2)
Write signal
Input sampling
timing
ADF
t
D
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
t : A/D conversion start delay
D
t : Input sampling time
SPL
t : A/D conversion time
CONV

Figure 16.2 A/D Conversion Timing

) has passed after the ADST bit is set to 1, then
D
and the input sampling time. The
D
t
SPL
t
CONV