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19.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t
after the ADST bit is set to 1, then starts conversion. Figure 19-5 shows the A/D
D
conversion timing. Table 19-4 indicates the A/D conversion time.
As indicated in figure 19-5, the A/D conversion time includes t
length of t
varies depending on the timing of the write access to ADCSR. The total conversion
D
time therefore varies within the ranges indicated in table 19-4.
In scan mode, the values given in table 19-4 apply to the first conversion time. The values given
in table 19-5 apply to the second and subsequent conversions. In both cases, set bits CKS1 and
CKS0 in ADCR to give a conversion time of at least 10 µs when AV
when AV
< 4.5 V.
CC
ø
Address
Write signal
Input sampling
timing
ADF
Legend
(1)
: ADCSR write cycle
(2)
: ADCSR address
t
: A/D conversion start delay
D
t
: Input sampling time
SPL
t
: A/D conversion time
CONV
874
(1)
(2)
t
t
D
SPL
Figure 19-5 A/D Conversion Timing
and the input sampling time. The
D
≥ 4.5 V, and at least 16 µs
CC
t
CONV
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