Input Sampling And A/D Conversion Time - Renesas H8S Series Hardware Manual

16.4.3

Input Sampling and A/D Conversion Time

The A/D converter has a on-chip sample-and-hold circuit. The A/D converter samples the analog input at a time t
the ADST bit is set to 1, then starts conversion. Figure 16-5 shows the A/D conversion timing. Table 16-4 indicates the
A/D conversion time.
As indicated in figure 16-5, the A/D conversion time includes t
depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges
indicated in table 16-4.
In scan mode, the values given in table 16-4 apply to the first conversion time. In the second and subsequent conversions
the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1.
ø
Address bus
Write signal
Input sampling
timing
ADF
Table 16-4 A/D Conversion Time (Single Mode)
Item
A/D conversion start delay
Input sampling time
A/D conversion time
Note: Values in the table are the number of states.
(1)
(2)
t
D
Legend:
(1): ADCSR write cycle
(2): ADCSR address
t A/D conversion start delay
D:
t Input sampling time
SPL:
t A/D conversion time
CONV:
Figure 16-5 A/D Conversion Timing
Symbol
t
D
t
SPL
t
CONV
and the input sampling time. The length of t
D
t
SPL
t
CONV
CKS = 0
Min Typ Max
10 — 17
— 63 —
259 — 266
CKS = 1
Min Typ Max
6 — 9
— 31 —
131 — 134
Rev.6.00 Oct.28.2004 page 549 of 1016
REJ09B0138-0600H
after
D
varies
D