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4. The ADST bit is not cleared automatically, and steps [2] and [3] are repeated as long as the
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the
A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again
from the first channel in the group.
16.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when A/D conversion start delay time (t
conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 indicates the A/D
conversion time.
As indicated in figure 16.2, the A/D conversion time (t
(t
). The length of t
SPL
conversion time therefore varies within the ranges indicated in tables 16.3.
In scan mode, the values given in table 16.3 apply to the first conversion time. The values given
in table 16.4 apply to the second and subsequent conversions.
Address
Write signal
Input sampling
timing
ADF
Legend
(1)
(2)
t
D
t
SPL
t
CONV
varies depending on the timing of the write access to ADCSR. The total
D
(1)
(2)
t
D
: ADCSR write cycle
: ADCSR address
: A/D conversion start delay time
: Input sampling time
: A/D conversion time
Figure 16.2 A/D Conversion Timing
) passes after the ADST bit is set to 1, then starts
D
) includes t
CONV
t
SPL
t
CONV
Rev. 2.00, 05/03, page 627 of 820
and the input sampling time
D
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