Input Sampling And A/D Conversion Time; Figure 15.5 A/D Conversion Timing - Renesas H8SX/1520 Series Hardware Manual

15.4.3

Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
to 1, then starts A/D conversion. Figure 15.5 shows the A/D conversion timing. Table 15.3
indicates the A/D conversion time.
As indicated in figure 15.5, the A/D conversion time (t
(t ). The length of t
SPL
conversion time therefore varies within the ranges indicated in table 15.3.
In scan mode, the values given in table 15.3 apply to the first conversion time. The values given in
table 15.4 apply to the second and subsequent conversions. In either case, bits CKS1 and CKS0 in
ADCR should be set so that the conversion time is within the ranges indicated by the A/D
conversion characteristics.
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varies depending on the timing of the write access to ADCSR. The total
D
(1)
Pφ
Address (2)
Write signal
Input sampling
timing
ADF
t
D
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
t : A/D conversion start delay time
D
t : Input sampling time
SPL
t : A/D conversion time
CONV

Figure 15.5 A/D Conversion Timing

) passes after the ADST bit in ADCSR is set
D
) includes t
CONV
t
SPL
t
CONV
Rev. 3.00 Mar. 14, 2006 Page 559 of 804
Section 15 A/D Converter
and the input sampling time
D
REJ09B0104-0300