Register Descriptions; System Clock Control Register (Sckcr) - Renesas H8S Series Hardware Manual

Section 19 Clock Pulse Generator
19.1

Register Descriptions

The on-chip clock pulse generator has the following registers. For details on register addresses,
refer to appendix A, On-Chip I/O Register.

• System clock control register (SCKCR)

• Low-power control register (LPWRCR)
19.1.1 System Clock Control Register (SCKCR)
SCKCR performs φ clock output control, selection of operation when the PLL circuit frequency
multiplication factor is changed, and medium-speed mode control.
Bit Bit Name
7 PSTOP
6 to —
4
Rev. 6.00 Mar 15, 2006 page 482 of 570
REJ09B0211-0600
Initial Value R/W
0 R/W
All 0 —
Description
φ Clock Output Disable
Controls φ output.
High-speed Mode, Medium-Speed Mode
0: φ output
1: Fixed high
Sleep Mode
0: φ output
1: Fixed high
Software Standby Mode
0: Fixed high
1: Fixed high
Hardware Standby Mode
0: High impedance
1: High impedance
Reserved
These bits are always read as 0.