Register Descriptions; System Clock Control Register (Sckcr) - Renesas H8S Series Hardware Manual

20.2

Register Descriptions

20.2.1

System Clock Control Register (SCKCR)

Bit : 7
PSTOP
Initial value : 0
R/W : R/W
SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Note: * R/W in the H8S/2390, H8S/2392, H8S/2394 and H8S/2398.
Bit 7—ø Clock Output Disable (PSTOP): Controls ø output.
Bit 7
PSTOP
0
1
Bit 6—Reserved: This bit can be read or written to, but only 0 should be written.
Bit 5—Reserved: In the H8S/2357 and H8S/2352, this bit cannot be modified and is always read as 0. Only 0 should be
written. This bit is reserved in the H8S/2390, H8S/2392, H8S/2394, and H8S/2398. Only 0 should be written to this bit.
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus master.
Bit 2 Bit 1
SCK2 SCK1
0 0
1
1 0
1
Rev.6.00 Oct.28.2004 page 662 of 1016
REJ09B0138-0600H
6 5
— —
0 0
R/W —/(R/W)*
Normal Operation
ø output (initial value)
Fixed high
Bit 0
SCK0 Description
0 Bus master is in high-speed mode
1 Medium-speed clock is ø/2
0 Medium-speed clock is ø/4
1 Medium-speed clock is ø/8
0 Medium-speed clock is ø/16
1 Medium-speed clock is ø/32
— —
4 3 2
— — SCK2
0 0 0
— — R/W
Description
Software
Sleep Mode Standby Mode
ø output Fixed high
Fixed high Fixed high
1 0
SCK1 SCK0
0 0
R/W R/W
Hardware
Standby Mode
High impedance
High impedance
(Initial value)