Renesas Hitachi H8S/2194 Series Hardware Manual page 997

H'D11F: Timer R Control/Status Register TMRCS: Timer R
7
Bit :
TMRI3E
0
Initial value :
R/W
R/W :
TMRI3 interrupt enable bit
0
1
Note: * Only 0 can be written to clear the flag.
Rev. 2.0, 11/00, page 970 of 1037
6 5
TMRI2E TMRI1E TMRI3
0 0
R/(W) *
R/W R/W
TMRI3 interrupt request flag
0
1
TMRI1 interrupt enable bit
0 TMRI1 interrupt request is disabled
1 TMRI1 interrupt request is enabled
TMRI2 interrupt enable bit
0 TMRI2 interrupt request is disabled
1 TMRI2 interrupt request is enabled
TMRI3 interrupt request is disabled
TMRI3 interrupt request is enabled
4 3 2
TMRI2 TMRI1
0 0 0
R/(W) * R/(W) *
TMRI1 interrupt request flag
0
1
TMRI2 interrupt request flag
0 [Clearing conditions]
When 0 is written after reading 1
1 [Setting conditions]
When TMRU-2 underflows or when capstan motor
acceleration/deceleration operation ends
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When interrupt source selected at CP/SLM bit in
TMRM2 is generated
1 0
— —
1 1
— —
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When TMRU-1 underflows