Renesas Hitachi H8S/2194 Series Hardware Manual page 995

H'D119: Timer R Mode Register TMRM2: Timer R
7
Bit :
LAT
0
Initial value :
R/W
R/W :
TMRU-1 clock source select bits
TMRU-2 captrue signal select bits
LAT
0
1
Note: * Don't care.
Note: Only 0 can be written to clear the flag.
*
Rev. 2.0, 11/00, page 968 of 1037
6 5
PS11 PS10
0 0
R/W R/W
Capture signal flag
0
1
Interrupt select bit
0 Interrupt request by TMRU-2 capture signal is enabled
1 Interrupt request by slow tracking mono-multi end is enabled
TMRU-3 clock source select bits
PS31 PS30
0 0
1
1 0
1
PS11 PS10 TMRU-1 clock source select
0 0 Count at CFG rising edge
PSS, count at φ/4
1
PSS, count at φ/256
1 0
PSS, count at φ/512
1
CPS TMRU-2 capture signal select
Capture at TMRU-3 underflow
*
0 Capture at CFG rising edge
1 Capture at IRQ3 edge
4 3
PS31 PS30 CP/SLM
0 0
R/W R/W R/W
Slow tracking mono-multi flag
0 [Clearing conditions]
When 0 is written after reading 1
1 [Setting conditions]
When slow tracking mono-multi ends while
CP/SLM bit = 1
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When TMRU-2 capture signal is generated while CP/SLM bit = 0
TMRU-3 clock source select
Count at rising edge of DVCTL from frequency divider
PSS, count at φ/4096
PSS, count at φ/2048
PSS, count at φ/1024
2 1 0
CAPF SLW
0 0 0
R/(W) * R/(W) *