Renesas Hitachi H8S/2194 Series Hardware Manual page 992

H'D111: Timer Load RegisterB TLB: TimerB
Bit :
7
TLB17
Initial value : 0
R/W : W
H'D112: Timer L Mode Register LMR: Timer L
Bit : 7
LMIF
0
Initial value :
R/(W) *
R/W :
Timer L interrupt request flag
0
1
Note: Only 0 can be written to clear the flag.
*
6 5
TLB16 TLB15 TLB14
0 0
W W
6 5
LMIE
—
0 1
R/W —
Clock select bit
R2
0
1
Note: * Don't care.
Up/down count control
0 Up count control
1 Down count control
Timer L interrupt enable bit
0 Timer L interrupt request is disabled
1 Timer L interrupt request is enabled
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When LTC overflow, underflow or compare
match clear occurs
4 3 2
TLB13 TLB12
0 0 0
W W W
4 3 2
IMR3 IMR2
—
1 0 0
— R/W R/W
LMR1 LMR0
0 0 Count at rising edge of PB and REC-CTL
1 Count at falling edge of PB and REC-CTL
1 Count DVCFG2
*
Internal clock: Count at φ/128
0
*
Internal clock: Count at φ/64
1
*
Rev. 2.0, 11/00, page 965 of 1037
1 0
TLB11 TLB10
0 0
W W
1 0
IMR1 IMR0
0 0
R/W R/W
Clock select