Renesas H8S/2117R Series Manuals

Manuals and User Guides for Renesas H8S/2117R Series. We have 1 Renesas H8S/2117R Series manual available for free PDF download: Hardware Manual

Renesas H8S/2117R Series Hardware Manual (1024 pages)

16-Bit Single-Chip Microcomputer

Brand: Renesas | Category: Computer Hardware | Size: 6.38 MB

Table of Contents
9
Section 1 Overview

27
- Features
  27
  - Applications
    27
  - Overview of Functions
    28
- List of Products
  33
- Block Diagram
  34
- Pin Descriptions
  35
  - Pin Assignments
    35
  - Pin Assignment in each Operating Mode
    38
  - Pin Functions
    45
Section 2 CPU

55
Section 3 MCU Operating Modes

93
- Operating Mode Selection
  93
- Register Descriptions
  94
- Operating Mode Descriptions
  99
  - Mode 2
    99
- Address Map
  100
Section 4 Exception Handling

101
- Exception Handling Types and Priority
  101
- Exception Sources and Exception Vector Table
  102
- Reset
  105
- Interrupt Exception Handling
  107
- Trap Instruction Exception Handling
  107
- Exception Handling by Illegal Instruction
  108
- Stack Status after Exception Handling
  109
- Usage Note
  110
Section 5 Interrupt Controller

111
Section 6 Bus Controller (BSC)

159
- Register Descriptions
  159
  - Bus Control Register (BCR)
    159
  - Wait State Control Register (WSCR)
    160
Section 7 I/O Ports

161
- Register Descriptions
  169
- Output Buffer Control
  180
  - Port 1
    180
  - Port 2
    180
  - Port 3
    181
  - Port 4
    181
  - Port 5
    185
  - Port 6
    187
  - Port 7
    188
  - Port 8
    189
  - Port 9
    192
  - Port a
    194
  - Port B
    195
  - Port C
    199
  - Port D
    203
  - Port E
    203
  - Port F
    204
  - Port G
    207
  - Port H
    211
  - Port I
    213
  - Port J
    213
- Change of Peripheral Function Pins
  220
Section 8 8-Bit PWM Timer (PWMU)

223
- Features
  223
- Input/Output Pins
  225
- Register Descriptions
  226
- Operation
  236
  - Single-Pulse Mode (8 Bits, 16 Bits)
    236
  - Pulse Division Mode
    240
- Usage Note
  243
  - Setting Module Stop Mode
    243
  - Note on Using 16-Bit Single-Pulse PWM Timer
    243
Section 9 14-Bit PWM Timer (PWMX)

245
- Features
  245
- Input/Output Pins
  246
- Register Descriptions
  246
- Bus Master Interface
  252
- Operation
  255
- Usage Notes
  262
  - Module Stop Mode Setting
    262
Section 10 16-Bit Timer Pulse Unit (TPU)

263
- Features
  263
- Input/Output Pins
  267
- Register Descriptions
  268
  - Timer Control Register (TCR)
    269
  - Timer Mode Register (TMDR)
    273
  - Timer I/O Control Register (TIOR)
    275
  - Timer Interrupt Enable Register (TIER)
    284
  - Timer Status Register (TSR)
    286
  - Timer Counter (TCNT)
    289
  - Timer General Register (TGR)
    289
  - Timer Start Register (TSTR)
    289
  - Timer Synchro Register (TSYR)
    290
- Interface to Bus Master
  291
  - 16-Bit Registers
    291
- Operation
  293
  - Basic Functions
    293
  - Synchronous Operation
    299
  - Buffer Operation
    301
  - PWM Modes
    305
  - Phase Counting Mode
    309
- Interrupts
  314
  - Interrupt Source and Priority
    314
  - A/D Converter Activation
    315
- Operation Timing
  316
  - Input/Output Timing
    316
  - Interrupt Signal Timing
    320
- Usage Notes
  323
Section 11 16-Bit Cycle Measurement Timer (TCM)

331
Section 12 16-Bit Duty Period Measurement Timer (TDP)

355
Section 13 8-Bit Timer (TMR)

381
- Features
  381
- Input/Output Pins
  384
- Register Descriptions
  385
- Operation
  401
  - Pulse Output
    401
- Operation Timing
  402
- TMR_0 and TMR_1 Cascaded Connection
  406
  - 16-Bit Count Mode
    406
  - Compare-Match Count Mode
    406
- TMR_Y and TMR_X Cascaded Connection
  407
  - 16-Bit Count Mode
    407
  - Compare-Match Count Mode
    407
  - Input Capture Operation
    408
- Interrupt Sources
  410
- Usage Notes
  411
Section 14 Watchdog Timer (WDT)

417
- Features
  417
- Input/Output Pins
  419
- Register Descriptions
  419
  - Timer Counter (TCNT)
    420
  - Timer Control/Status Register (TCSR)
    420
- Operation
  424
  - Watchdog Timer Mode
    424
  - Interval Timer Mode
    425
- Interrupt Sources
  426
- Usage Notes
  426
Section 15 Serial Communication Interface (SCI)

429
Section 16 CIR Interface

495
Section 17 Serial Communication Interface with FIFO (SCIF)

519
- Features
  519
- Input/Output Pins
  521
- Register Descriptions
  522
  - Receive Shift Register (FRSR)
    523
  - Receive Buffer Register (FRBR)
    523
  - Transmitter Shift Register (FTSR)
    524
  - Transmitter Holding Register (FTHR)
    524
  - Divisor Latch H, L (FDLH, FDLL)
    524
  - Interrupt Enable Register (FIER)
    525
  - Interrupt Identification Register (FIIR)
    526
  - FIFO Control Register (FFCR)
    528
  - Line Control Register (FLCR)
    529
  - Modem Control Register (FMCR)
    530
  - Line Status Register (FLSR)
    532
  - Modem Status Register (FMSR)
    536
  - Scratch Pad Register (FSCR)
    537
  - SCIF Control Register (SCIFCR)
    538
- Operation
  540
- Interrupt Sources
  554
- Usage Note
  554
  - Power-Down Mode When LCLK Is Selected for SCLK
    554
Section 18 I C Bus Interface (IIC)

555
- Features
  555
- Input/Output Pins
  559
- Register Descriptions
  560
  - C Bus Data Register (ICDR)
    562
  - Slave Address Register (SAR)
    563
  - Second Slave Address Register (SARX)
    564
  - C Bus Mode Register (ICMR)
    566
  - C Bus Control Register (ICCR)
    569
  - C Bus Status Register (ICSR)
    577
  - C Bus Control Initialization Register (ICRES)
    581
  - C Bus Extended Control Register (ICXR)
    582
- Operation
  586
  - C Bus Data Format
    586
  - Initialization
    588
  - Master Transmit Operation
    588
  - Master Receive Operation
    593
  - Slave Receive Operation
    596
  - Slave Transmit Operation
    600
  - IRIC Setting Timing and SCL Control
    603
  - Noise Canceler
    605
  - Initialization of Internal State
    605
- Interrupt Sources
  607
- Usage Notes
  608
  - Module Stop Mode Setting
    611
Section 19 Keyboard Buffer Control Unit (PS2)

613
- Features
  613
- Input/Output Pins
  615
- Register Descriptions
  616
- Operation
  625
  - Receive Operation
    625
  - Transmit Operation
    627
  - Receive Abort
    628
  - KCLKI and KDI Read Timing
    631
  - KCLKO and KDO Write Timing
    631
  - KBF Setting Timing and KCLK Control
    632
  - Receive Timing
    633
  - Operation During Data Reception
    633
  - KCLK Fall Interrupt Operation
    634
  - 19.4.10 First KCLK Falling Interrupt
    635
- Usage Notes
  639
Section 20 LPC Interface (LPC)

641
Section 21 FSI Interface

707
Section 22 A/D Converter

753
- Features
  753
- Input/Output Pins
  755
- Register Descriptions
  756
- Operation
  761
  - Single Mode
    761
  - Scan Mode
    762
  - Input Sampling and A/D Conversion Time
    763
- Interrupt Source
  765
- A/D Conversion Accuracy Definitions
  765
- Usage Notes
  767
Section 23 RAM

773
Section 24 Flash Memory

775
- Features
  775
- Mode Transition Diagram
  776
- Flash Memory MAT Configuration
  778
- Block Structure
  779
- Programming/Erasing Interface
  780
- Input/Output Pins
  782
- Register Descriptions
  783
  - Programming/Erasing Interface Registers
    785
  - Programming/Erasing Interface Parameters
    791
- On-Board Programming Mode
  802
  - Boot Mode
    802
  - User Program Mode
    806
  - User Boot Mode
    815
  - Storable Areas for On-Chip Program and Program Data
    819
- Protection
  824
  - Hardware Protection
    824
  - Software Protection
    825
  - Error Protection
    825
- Switching between User MAT and User Boot MAT
  827
- Programmer Mode
  828
- Standard Serial Communication Interface Specifications for Boot Mode
  828
- Usage Notes
  857
Section 25 Clock Pulse Generator

859
- Oscillator
  860
  - Connecting Crystal Resonator
    860
  - External Clock Input Method
    861
- Duty Correction Circuit
  864
- Subclock Input Circuit
  864
- Subclock Waveform Forming Circuit
  865
- Clock Select Circuit
  865
- Usage Notes
  866
  - Notes on Resonator
    866
  - Notes on Board Design
    866
Section 26 Power-Down Modes

867
- Register Descriptions
  867
- Mode Transitions and LSI States
  874
- Medium-Speed Mode
  876
- Sleep Mode
  877
- Software Standby Mode
  877
- Watch Mode
  879
- Module Stop Mode
  880
- Usage Notes
  880
  - I/O Port Status
    880
  - Current Consumption When Waiting for Oscillation Stabilization
    880
Section 27 List of Registers

881
Section 28 Electrical Characteristics

983
- Absolute Maximum Ratings
  983
- DC Characteristics
  984
- AC Characteristics
  989
  - Clock Timing
    990
  - Control Signal Timing
    992
  - Timing of On-Chip Peripheral Modules
    994
- A/D Conversion Characteristics
  1005
- Flash Memory Characteristics
  1006
- Usage Notes
  1007
Appendix

1009
- I/O Port States in each Pin State
  1009
- Product Lineup
  1010
- Package Dimensions
  1011
- Treatment of Unused Pins
  1014
Index

1015

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Renesas H8S/2117R Series Manuals

Renesas H8S/2117R Series Hardware Manual (1024 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller (BSC)

Section 7 I/O Ports

Section 8 8-Bit PWM Timer (PWMU)

Section 9 14-Bit PWM Timer (PWMX)

Section 10 16-Bit Timer Pulse Unit (TPU)

Section 11 16-Bit Cycle Measurement Timer (TCM)

Section 12 16-Bit Duty Period Measurement Timer (TDP)

Section 13 8-Bit Timer (TMR)

Section 14 Watchdog Timer (WDT)

Section 15 Serial Communication Interface (SCI)

Section 16 CIR Interface

Section 17 Serial Communication Interface with FIFO (SCIF)

Section 18 I C Bus Interface (IIC)

Section 19 Keyboard Buffer Control Unit (PS2)

Section 20 LPC Interface (LPC)

Section 21 FSI Interface

Section 22 A/D Converter

Section 23 RAM

Section 24 Flash Memory

Section 25 Clock Pulse Generator

Section 26 Power-Down Modes

Section 27 List of Registers

Section 28 Electrical Characteristics

Appendix

Index

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