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6. ROM
6.5
Flash Memory Programming/Erasing
A software method, using the CPU, is employed to program and erase flash memory in the on-
board programming modes. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by
setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1.
The flash memory cannot be read while being programmed or erased. Therefore, the program that
controls flash memory programming/erasing (the programming control program) should be placed
in on-chip RAM, and executed there.
See section 6.9, Flash Memory Programming and Erasing Precautions, for points to note
concerning programming and erasing, and section 15.2.6, Flash Memory Characteristics, for the
wait times after setting or clearing FLMCR1 and FLMCR2 bits.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, EV, PV, E, and P bits in
FLMCR1 and the ESU and PSU bits in FLMCR2 is executed by a program in flash
memory.
2. When programming or erasing, set FWE to 1 (programming/erasing will not be
executed if FWE = 0).
3. Programming should be performed in the erased state. Do not perform additional
programming on addresses that have already been programmed.
6.5.1
Program Mode
When writing data or programs to flash memory, the program/program-verify flowchart shown in
figure 6.12 should be followed. Performing programming operations according to this flowchart
will enable data or programs to be written to flash memory without subjecting the device to
voltage stress or sacrificing programming data reliability. Programming should be carried out 32
bytes at a time.
The wait times (x, y, z, α, β, γ, ε, η) after bits are set or cleared in flash memory control register 1
(FLMCR1) and flash memory control register 2 (FLMCR2), and the maximum number of
programming operations (N), are shown in table 15.10 in section 15.2.6, Flash Memory
Characteristics.
Following the elapse of (x) μs or more after the SWE bit is set to 1 in FLMCR1, 32-byte
programming data is stored in the programming data area and the reprogramming data area, and
the 32 bytes of data in the reprogramming data area in RAM are written consecutively to the write
addresses. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80,
H'A0, H'C0, or H'E0. Thirty-two consecutive byte data transfers are performed. The programming
address and programming data are latched in the flash memory. A 32-byte data transfer must be
Rev.3.00 Jul. 19, 2007 page 140 of 532
REJ09B0397-0300
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