Irq Status Register (Isr) - Renesas H8S/2368 Series Hardware Manual

5.3.5

IRQ Status Register (ISR)

ISR is an IRQ7 to IRQ0 interrupt request flag register.
Bit
Bit Name
−
15 to 8
7 IRQ7F
6 IRQ6F
5 IRQ5F
4 IRQ4F
3 IRQ3F
2 IRQ2F
1 IRQ1F
0 IRQ0F
Note: * Only 0 can be written, to clear the flag.
Rev. 2.00, 05/03, page 88 of 820
Initial Value R/W
0 R/W
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
Description
Reserved
The write value should always be 0.
[Setting conditions]
When the interrupt source selected by ISCR
occurs
[Clearing conditions]
•
Cleared by reading IRQnF flag when IRQnF
= 1, then writing 0 to IRQnF flag
•
When interrupt exception handling is
executed when low-level detection is set
and IRQn input is high
•
When IRQn interrupt exception handling is
executed when falling, rising, or both-edge
detection is set
•
When the DTC is activated by an IRQn
interrupt, and the DISEL bit in MRB of the
DTC is cleared to 0