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Section 5 Interrupt Controller
5.3.6
IRQ Status Register (ISR)
ISR is an IRQ11 to IRQ0 interrupt request register.
Bit
15
Bit Name
Initial Value
0
R/W
R/W
Bit
7
Bit Name
IRQ7F
Initial Value
0
R/W
R/(W)*
Note: *
Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should
be used to clear the flag.
Bit
Bit Name
15 to 12
11
IRQ11F
10
IRQ10F
9
IRQ9F
8
IRQ8F
7
IRQ7F
6
IRQ6F
5
IRQ5F
4
IRQ4F
3
IRQ3F
2
IRQ2F
1
IRQ1F
0
IRQ0F
Note:
*
Only 0 can be written, to clear the flag.
Rev.2.00 Jun. 28, 2007 Page 98 of 666
REJ09B0311-0200
14
13
0
0
R/W
R/W
6
5
IRQ6F
IRQ5F
0
0
R/(W)*
R/(W)*
Initial
Value
R/W
Description
All 0
R/W
Reserved
These bits are always read as 0. The write value should
always be 0.
0
R/(W)*
[Setting condition]
•
0
R/(W)*
0
R/(W)*
[Clearing conditions]
•
0
R/(W)*
•
0
R/(W)*
0
R/(W)*
•
0
R/(W)*
0
R/(W)*
0
R/(W)*
•
0
R/(W)*
0
R/(W)*
0
R/(W)*
12
11
IRQ11F
0
0
R/W
R/(W)*
4
3
IRQ4F
IRQ3F
0
0
R/(W)*
R/(W)*
When the interrupt selected by ISCR occurs
Writing 0 after reading IRQnF = 1
When interrupt exception handling is executed when
low-level sensing is selected and IRQn input is high
When IRQn interrupt exception handling is executed
when falling-, rising-, or both-edge sensing is
selected
When the DTC is activated by an IRQn interrupt,
and the DISEL bit in MRB of the DTC is cleared to 0
10
9
IRQ10F
IRQ9F
0
0
R/(W)*
R/(W)*
2
1
IRQ2F
IRQ1F
0
0
R/(W)*
R/(W)*
8
IRQ8F
0
R/(W)*
0
IRQ0F
0
R/(W)*
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