Irq Status Register (Isr) - Renesas H8SX/1520 Series Hardware Manual

5.3.6

IRQ Status Register (ISR)

ISR is an IRQ14 to IRQ0 interrupt request register.
Bit
Bit Name
Initial Value
R/W R/(W)*
Bit
Bit Name IRQ7F
Initial Value
R/W R/(W)*
Note: * Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should
be used to clear the flag.
Bit Bit Name

15
14 IRQ14F
13 IRQ13F
12 IRQ12F
11 IRQ11F
10 IRQ10F
9 IRQ9F
8 IRQ8F
7 IRQ7F
6 IRQ6F
5 IRQ5F
4 IRQ4F
3 IRQ3F
2 IRQ2F
1 IRQ1F
0 IRQ0F
Note: * Only 0 can be written, to clear the flag. The bit manipulation instructions or memory
operation instructions should be used to clear the flag.
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15 14 13
— IRQ14F IRQ13F
0 0
R/(W)* R/(W)*
7 6
IRQ6F IRQ5F
0 0
R/(W)* R/(W)*
Initial
Value R/W
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
12 11
IRQ12F IRQ11F
0 0 0
R/(W)* R/(W)*
5 4 3
IRQ4F IRQ3F
0 0 0
R/(W)* R/(W)*
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
[Setting condition]
•
When the interrupt selected by ISCR occurs
[Clearing conditions]
•
Writing 0 after reading IRQnF = 1
•
When interrupt exception handling is executed when
low-level sensing is selected and IRQn input is high
•
When IRQn interrupt exception handling is executed
when falling-, rising-, or both-edge sensing is
selected
Section 5 Interrupt Controller
10 9
IRQ10F IRQ9F
0 0
R/(W)* R/(W)*
2 1
IRQ2F IRQ1F
0 0
R/(W)* R/(W)*
Rev. 3.00 Mar. 14, 2006 Page 101 of 804
REJ09B0104-0300
8
IRQ8F
0
R/(W)*
0
IRQ0F
0
R/(W)*