Ss Enable Register (Sser) - Renesas H8SX/1520 Series Hardware Manual

Section 14 Synchronous Serial Communication Unit (SSU)
14.3.4

SS Enable Register (SSER)

SSER performs transfer/receive control of synchronous serial communication and setting of
interrupt enable.
Bit
Bit Name
Initial Value
R/W
Bit Bit Name
7 TE
6 RE

5, 4
3 TEIE
2 TIE
1 RIE
0 CEIE
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7 6 5
TE RE —
0 0 0
R/W R/W R/W
Initial
Value R/W
0 R/W
0 R/W
All 0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
4 3
— TEIE
0 0
R/W R/W
Description
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
Receive Interrupt Enable
When this bit is set to 1, an RXI interrupt request and
an OEI interrupt request are enabled.
Conflict Error Interrupt Enable
When this bit is set to 1, a CEI interrupt request is
enabled.
2 1 0
TIE RIE CEIE
0 0 0
R/W R/W R/W