ST STM32L4+ Series Reference Manual page 1345

RM0432
1. Configure TIM3 master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIM3_CR2 register).
2. Configure the TIM3 period (TIM3_ARR registers).
3. Configure TIM2 to get the input trigger from TIM3 (TS=010 in the TIM2_SMCR
register).
4. Configure TIM2 in trigger mode (SMS=110 in TIM2_SMCR register).
5. Start TIM3 by writing '1 in the CEN bit (TIM3_CR1 register).
TIM2-CEN=CNT_EN
As in the previous example, both counters can be initialized before starting counting.
Figure 391
mode instead of gated mode (SMS=110 in the TIM2_SMCR register).
TIM3-CEN=CNT_EN
Starting 2 timers synchronously in response to an external trigger
In this example, we set the enable of TIM3 when its TI1 input rises, and the enable of TIM2
with the enable of TIM3. Refer to
Figure 390. Triggering TIM2 with update of TIM3
CK_INT
TIM3-UEV
TIM3-CNT
TIM2-CNT
TIM2-TIF
shows the behavior with the same configuration as in
Figure 391. Triggering TIM2 with Enable of TIM3
CK_INT
TIM3-CNT_INIT
75
TIM3-CNT
TIM2-CNT
TIM2-CNT_INIT
TIM2
write CNT
TIM2-TIF
General-purpose timers (TIM2/TIM3/TIM4/TIM5)
FD FE FF
45
Write TIF = 0
00
CD 00 E7
Write TIF = 0
Figure 387 for connections. To ensure the counters are
RM0432 Rev 6
00 01 02
46 47 48
Figure 390
01 02
E9
E8 EA
MS33121V1
but in trigger
MS33122V1
1345/2301
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