Central Processing Unit (Cpu); Data Registers (R0, R1, R2, And R3); Address Registers (A0 And A1) - Renesas M16C/60 Series Hardware Manual

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group

Central Processing Unit (CPU)

Figure 1.3.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31
Note: These registers comprise a register bank. There are two register banks.
Figure 1.3.1 CPU Registers

(1) Data Registers (R0, R1, R2, and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit
data register (R2R0). R3R1 is the same as R2R0.

(2) Address Registers (A0 and A1)

The A0 register consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the
same as A0.
In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Rev.1.00 2003.05.30 page 9
b15
R2 R0H (R0's high bits) R0L (R0's low bits)
R3 R1H (R1's high bits) R1L (R1's low bits)
b19
INTBH
The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.
b19
b15
b15
b15 b8 b7
IPL U
b8 b7 b0
Data registers (Note)
R2
R3
A0
Address registers (Note)
A1
FB
Frame base registers (Note)
b0
Interrupt table register
INTBL
b0
Program counter
PC
b0
USP User stack pointer
ISP Interrupt stack pointer
Static base register
SB
b0
FLG
Flag register
b0
I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
CPU