7.5 Control Registers
7.5.1 DMA source address registers 0 to 3 (DSA0 to DSA3)
These registers are used to set the DMA transfer source addresses (28 bits each) for DMA channels n (n = 0 to 3).
They are divided into two 16-bit registers, DSAnH and DSAnL, respectively.
Since they are two-stage FIFO-configuration buffer registers, the transfer source address of a new DMA transfer
can be set during a DMA transfer (See 7.6 Next Address Setting Function).
When a flyby transfer is set according to the TTYP bit of the DMA addressing control registers n (DADCn), the
external memory addresses are set by the DSAn registers. At this time, any settings of the DMA destination address
registers n (DDAn) are ignored.
(1) DMA source address registers 0H to 3H (DSA0H to DSA3H)
These registers can be read or written in 16-bit units.
Figure 7-1. DMA Source Address Registers 0H to 3H (DSA0H to DSA3H)
15
14
13
DSA0H
IR
0
0
DSA1H
IR
0
0
DSA2H
IR
0
0
DSA3H
IR
0
0
Bit position
Bit name
15
IR
11 to 0
SA27 to
SA16
Caution Bits 14 to 12 of the DSA0H to DSA3H registers must be set to 0. The operation when these
bits are set to 1 is not guaranteed.
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CHAPTER 7 DMAC
12
11
10
9
8
7
SA
SA
SA
SA
SA
0
27
26
25
24
23
SA
SA
SA
SA
SA
0
27
26
25
24
23
SA
SA
SA
SA
SA
0
27
26
25
24
23
SA
SA
SA
SA
SA
0
27
26
25
24
23
Specifies the DMA transfer source.
0: External memory or peripheral macro
1: RAM
Sets the DMA transfer source address (A27 to A16). During a DMA transfer, the next DMA
transfer source address is maintained. For a flyby transfer, the external memory address is
maintained.
Preliminary User's Manual A14874EJ3V0UM
6
5
4
3
2
1
SA
SA
SA
SA
SA
SA
22
21
20
19
18
17
SA
SA
SA
SA
SA
SA
22
21
20
19
18
17
SA
SA
SA
SA
SA
SA
22
21
20
19
18
17
SA
SA
SA
SA
SA
SA
22
21
20
19
18
17
Function
0
SA
Address
After reset
16
FFFFF082H
Undefined
SA
Address
After reset
16
FFFFF08AH
Undefined
SA
Address
After reset
16
FFFFF092H
Undefined
SA
Address
After reset
16
FFFFF09AH
Undefined