Memory Address Registers (Mara And Marb); Table 7.2 Short Address Mode And Full Address Mode (Channel 0) - Renesas H8S/2368 Series Hardware Manual

• DMA band control register H (DMABCRH)
• DMA band control register L (DMABCRL)
• DMA write enable register (DMAWER)
• DMA terminal control register (DMATCR)
The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer
mode (short address mode or full address mode). The transfer mode can be selected by means of
the FAE1 and FAE0 bits in DMABCRH. The register configurations for short address mode and
full address mode of channel 0 are shown in table 7.2.
Table 7.2 Short Address Mode and Full Address Mode (Channel 0)
FAE0 Description
0 Short address mode specified (channels 0A and 0B operate independently)
MAR_0AH
MAR_0BH
1 Full address mode specified (channels 0A and 0B operate in combination as channel 0)
MAR_0AH
MAR_0BH
7.3.1

Memory Address Registers (MARA and MARB)

MAR is a 32-bit readable/writable register that specifies the source address (transfer source
address) or destination address (transfer destination address). MAR consists of two 16-bit registers
MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and
cannot be modified.
The DMA has four MAR registers: MAR_0A in channel 0 (channel 0A), MAR_0B in channel 0
(channel 0B), MAR_1A in channel 1 (channel 1A), and MAR_1B in channel 1 (channel 1B).
Rev. 2.00, 05/03, page 202 of 820
MAR_0AL
IOAR_0A
ETCR_0A
DMACR_0A
MAR_0BL
IOAR_0B
ETCR_0B
DMACR_0B
MAR_0AL
MAR_0BL
IOAR_0A
IOAR_0B
ETCR_0A
ETCR_0B
DMACR_0A DMACR_0B
Specifies transfer source/transfer destination address
Specifies transfer destination/transfer source address
Specifies number of transfers
Specifies transfer size, mode, activation source
Specifies transfer source/transfer destination address
Specifies transfer destination/transfer source address
Specifies number of transfers
Specifies transfer size, mode, activation source
Specifies transfer source address
Specifies transfer destination address
Not used
Not used
Specifies number of transfers
Specifies number of transfers (used in block transfer
mode only)
Specifies transfer size, mode, activation source, etc.