Memory Address Registers (Mar) - Renesas H8S/2633 Series Hardware Manual

8.2.1

Memory Address Registers (MAR)

Bit : 31
MAR : —
Initial value : 0
R/W : —
Bit : 15
MAR :
Initial value : *
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MAR is a 32-bit readable/writable register that specifies the transfer source address or destination
address.
The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified.
Whether MAR functions as the source address register or as the destination address register can be
selected by means of the DTDIR bit in DMACR.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
address specified by MAR is constantly updated. For details, see section 8.2.4, DMA Control
Register (DMACR).
MAR is not initialized by a reset or in standby mode.
248
30 29 28 27 26
— — — — —
0 0 0 0
— — — — —
14 13 12 11 10
* * * *
25 24 23 22
— —
0 0 0
* *
— — R/W R/W R/W R/W R/W R/W R/W R/W
9 8 7 6
* * * * *
21 20 19 18 17
* * * *
5 4 3 2
* * * *
*: Undefined
16
* *
1 0
* *