Bus Mode Control Register - Renesas M32R/ECU Series User Manual

15

15.2.3 Bus Mode Control Register

Bus Mode Control Register (BUSMODC)
b8 9 10
0 0 0
b Bit Name
8–14 No function assigned. Fix to "0".
15 BUSMOD
Bus mode control bit
This register is used to facilitate memory connections during processor mode and external extension mode.
When the Bus Mode Control bit (BUSMOD) = "0", the WR# signal is output separately for each byte area.
Signals RD#, BHW#, BLW#, BCLK# and WAIT# can be used.
When the Bus Mode Control bit (BUSMOD) = "1", the byte enable signal is output separately for each byte area.
Signals RD#, BHE#, BLE#, WR# and WAIT# can be used. In a WAIT control circuit configuration, because
BCLK output is not available, timing must be controlled external to the chip.
Note: • Any external bus area must temporarily be accessed for read or write before the Bus Mode
Control bit (BUSMOD) can be set to "1" (= byte enable separate mode).
For memory connection in boot mode, the Bus Mode Control Register has no effect, and the microcomputer
operates in the same way as when the Bus Mode Control bit (BUSMOD) is cleared to "0".
Figure 15.2.1 Pin Functions when External Bus Modes are Changed
11 12 13 14
BUSMOD
0 0 0 0
BUSMOD bit = 0
A11–A30
CS0#–CS3#
BCLK
RD#
BHW#
BLW#
DB0–DB15
WAIT#
EXTERNAL BUS INTERFACE
15.2 External Bus Interface Related Registers
b15
0
Function
0: WR signal separate mode
1: Byte enable separate mode
BUSMOD bit = 1
A11–A30
CS0#–CS3#
RD#
WR#
BHE#
BLE#
DB0–DB15
WAIT#
15-9
<Address: H'0080 077F>
<After reset: H'00>
R
0
R
32180 Group User's Manual (Rev.1.0)
W
0
W