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2
17.3.3
I
C Bus Mode Register (ICMR)
ICMR controls a wait in master mode and selects the transfer bit count.
Bit Bit Name
Initial Value R/W
7
0
6
WAIT
0
5
1
4
1
3
BCWP
1
Rev. 1.00, 09/03, page 482 of 704
Description
R/W
Reserved
The write value should always be 0.
R/W
Wait Insertion Bit
Selects whether to insert a wait after data transfer except
for the acknowledge bit in master mode. When the WAIT
bit is set to 1, after the fall of the clock for the last data bit,
low period is extended for two transfer clocks. If the WAIT
bit is cleared to 0, data and acknowledge bits are
transferred consecutively with no wait inserted.
The setting of this bit is invalid in slave mode.
Reserved
These bits are always read as 1.
R/W
BC Write Protect
Controls the BC2 to BC0 modifications. When modifying
the BC2 to BC0 bits, this bit should be cleared to 0 and use
the MOV instruction.
0: When writing, values of BC2 to BC0 are set.
1: When reading, 1 is always read.
When writing, settings of BC2 to BC0 are invalid.
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