I 2 C Bus Mode Register (Icmr) - Renesas H8S/2158 User Manual

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Section 17 I C Bus Interface (IIC)
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17.3.4 I C Bus Mode Register (ICMR)
ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit
in ICCR is set to 1.
Bit Bit Name Initial Value R/W
7 MLS 0
6 WAIT 0
5 CKS2 0
4 CKS1 0
3 CKS0 0
Rev. 3.00 Jan 25, 2006 page 482 of 872
REJ09B0286-0300
Description
R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
R/W Wait Insertion Bit
This bit is valid only in master mode with the I
format.
0: Data and the acknowledge bit are transferred
consecutively with no wait inserted.
1: After the fall of the clock for the final data bit, the IRIC
flag is set to 1 in ICCR, and a wait state begins (with
SCL at the low level). When the IRIC flag is cleared to
0 in ICCR, the wait ends and the acknowledge bit is
transferred.
For details, see section 17.5.6, IRIC Setting Timing and
SCL Control.
R/W Serial Clock Select 2 to 0
R/W These bits are valid only in master mode.
R/W These bits select the required transfer rate, together with
bit IICX1 (channel 1) or IICX0 (channel 0) in STCR. See
table 17.3.
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C bus format is used.
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C bus