C Bus Mode Register (Icmr) - Renesas H8S/2111B Hardware Manual

2
13.3.4 I

C Bus Mode Register (ICMR)

ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit
in ICCR is set to 1.
Bit Bit Name
7 MLS
6 WAIT
5 CKS2
4 CKS1
3 CKS0
Rev. 1.00, 05/04, page 286 of 544
Initial
Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
Wait Insertion Bit
This bit is valid only in master mode with the I
format.
0: Data and the acknowledge bit are transferred
consecutively with no wait inserted.
1: After the fall of the clock for the final data bit (8
clock), the IRIC flag is set to 1 in ICCR, and a wait
state begins (with SCL at the low level). When the
IRIC flag is cleared to 0 in ICCR, the wait ends and
the acknowledge bit is transferred.
For details, see section 13.4.7, IRIC Setting Timing and
SCL Control.
Transfer Clock Select 2 to 0
These bits are used only in master mode.
These bits select the required transfer rate, together with
the IICX1 (IIC_1) and IICX0 (IIC_0) bits in STCR. See
table 13.3.
2
C bus format is used.
2
C bus
th