Pwm Data Polarity Register (Pwdpr); Pwm Output Enable Register (Pwoer) - Renesas H8S/2437 Hardware Manual

8.3.3

PWM Data Polarity Register (PWDPR)

PWDPR selects the PWM output phase.
Bit Bit Name Initial Value
7 OS7 0
6 OS6 0
5 OS5 0
4 OS4 0
3 OS3 0
2 OS2 0
1 OS1 0
0 OS0 0
8.3.4

PWM Output Enable Register (PWOER)

PWOER switches between PWM output and port output.
Bit Bit Name Initial Value
7 OE7 0
6 OE6 0
5 OE5 0
4 OE4 0
3 OE3 0
2 OE2 0
1 OE1 0
0 OE0 0
[Legend]
n = 7 to 0
x: Don't care
To perform PWM 256/256 output when DDR = 1 and OE = 0, the corresponding pin should be set
to port output. The corresponding pin can be set as port output when IOSE = 1 and CS256E = 0 in
SYSCR in single-chip mode or in extended mode with on-chip ROM enabled. Otherwise, it
should be noted that an address bus is output to the corresponding pin.
DR data is output when the corresponding pin is used as port output. A value corresponding to
PWM 256/256 output is determined by the OS bit, so the value should be set to DR beforehand.
R/W Description
R/W Output Select 7 to 0
R/W
These bits select the PWM output phase. Bits OS7 to
R/W
OS0 correspond to outputs PW7 to PW0.
R/W
0: PWM direct output (PWDR value corresponds to high
R/W
width of output)
R/W
R/W
1: PWM inverted output (PWDR value corresponds to
R/W
low width of output)
R/W Description
R/W Output Enable 7 to 0
R/W
These bits, together with P1DDR, specify the P1n/PWn
R/W
pin state. Bits OE7 to OE0 correspond to outputs PW7
R/W
to PW0.
R/W
P1nDDR OEn: Pin state
R/W
R/W
0x: Port input
R/W
10: Port output or PWM 256/256 output
11: PWM output (0 to 255/256 output)
Rev. 1.00, 09/03, page 221 of 704