Next Address Setting Function; Buffer Register Configuration - Renesas NU85E Preliminary User's Manual

7.6 Next Address Setting Function

The DMA source address registers (DSAnH and DSAnL), DMA destination address registers (DDAnH and
DDAnL), and DMA transfer count registers (DBCn) are two-stage FIFO-configuration buffer registers (n = 0 to 3).
When a terminal count signal (DMTCOn) is output, these registers are automatically rewritten with the values that
had just been set before the signal is output.
Therefore, if a new DMA transfer is set for these registers during a DMA transfer, the transfer can begin only when
the ENn bit of the DCHCn register is set (1).
Figure 7-10 shows the buffer register configuration.
Reading of data
N
P
B
Writing of data
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CHAPTER 7 DMAC
Figure 7-10. Buffer Register Configuration
Master
register
Preliminary User's Manual A14874EJ3V0UM
Address/
Slave
count
register
controller