Serial Control Register (Scscr) - Renesas HD6417641 Hardware Manual

19.3.6

Serial Control Register (SCSCR)

The serial control register (SCSCR) operates the SCIF transmitter/receiver, enables/disables
interrupt requests, and selects the transmit/receive clock source. The CPU can always read and
write to SCSCR. SCSCR is initialized to H'0000 by a power-on reset.
Bit Bit Name

15 to 8
7 TIE
Section 19 Serial Communication Interface with FIFO (SCIF)
Initial
value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
0 R/W Transmit Interrupt Enable
Enables or disables the transmit-FIFO-data-empty
interrupt (TXI) requested when the serial transmit data
is transferred from the transmit FIFO data register
(SCFTDR) to the transmit shift register (SCTSR), when
the quantity of data in the transmit FIFO register
becomes less than the specified number of
transmission triggers, and when the TDFE flag in the
serial status register (SCFSR) is set to1.
0: Transmit-FIFO-data-empty interrupt request (TXI) is
disabled
1: Transmit-FIFO-data-empty interrupt request (TXI) is
enabled*
Note: * The TXI interrupt request can be cleared by
writing a greater quantity of transmit data than
the specified transmission trigger number to
SCFTDR and by clearing TDFE to 0 after
reading 1 from TDFE, or can be cleared by
clearing TIE to 0.
Rev. 4.00 Sep. 14, 2005 Page 695 of 982
REJ09B0023-0400