Host Interface Select Register (Hisel) - Renesas H8S/2111B Hardware Manual

15.4.2 LPC I/O Cycles
There are ten kinds of LPC transfer cycle: memory read, memory write, I/O read, I/O write, DMA
read, DMA write, bus master memory read, bus master memory write, bus master I/O read, and
bus master I/O write. Of these, the chip's LPC supports only I/O read and I/O write cycles.
An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state. If the
LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of
the LPC transfer cycle has been requested.
In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the
following order, in synchronization with LCLK. The host can be made to wait by sending back a
value other than B'0000 in the slave's synchronization return cycle, but with the chip's LPC a
value of B'0000 is always returned.
If the received address matches the host address in an LPC register (IDR, ODR, STR, TWR), the
host interface enters the busy state; it returns to the idle state by output of a state count 12
turnaround. Register and flag changes are made at this timing, so in the event of a transfer cycle
forced termination (abort) before state #12, registers and flags are not changed.
State
Count Contents
1 Start
2 Cycle type/direction Host
3 Address 1
4 Address 2
5 Address 3
6 Address 4
7 Turnaround
(recovery)
8 Turnaround
9 Synchronization
10 Data 1
11 Data 2
12 Turnaround
(recovery)
13 Turnaround
I/O Read Cycle
Drive Value
Source (3 to 0)
Host 0000
0000
Host Bits 15 to
12
Host Bits 11 to 8
Host Bits 7 to 4
Host Bits 3 to 0
Host 1111
None ZZZZ
Slave 0000
Slave Bits 3 to 0
Slave Bits 7 to 4
Slave 1111
None ZZZZ
I/O Write Cycle
Contents
Start
Cycle type/direction Host
Address 1
Address 2
Address 3
Address 4
Data 1
Data 2
Turnaround
(recovery)
Turnaround
Synchronization
Turnaround
(recovery)
Turnaround
Rev. 1.00, 05/04, page 397 of 544
Drive Value
Source (3 to 0)
Host 0000
0010
Host Bits 15 to
12
Host Bits 11 to 8
Host Bits 7 to 4
Host Bits 3 to 0
Host Bits 3 to 0
Host Bits 7 to 4
Host 1111
None ZZZZ
Slave 0000
Slave 1111
None ZZZZ