Burst Rom Interface Control Register (Bromcr) - Renesas H8SX/1650 Hardware Manual

Section 6 Bus Controller (BSC)
6.2.11

Burst ROM Interface Control Register (BROMCR)

BROMCR specifies the burst ROM interface.
Bit 15
Bit Name BSRM0
Initial Value 0
R/W R/W
Bit 7
Bit Name BSRM1
Initial Value 0
R/W R/W
Bit Bit Name
15 BSRM0
14 BSTS02
13 BSTS01
12 BSTS00

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REJ09B0311-0200
14 13
BSTS02 BSTS01
0 0
R/W R/W
6 5
BSTS12 BSTS11
0 0
R/W R/W
Initial
Value R/W Description
0 R/W Area 0 Burst ROM Interface Select
Selects the area 0 bus interface. When setting this bit to
1, clear the BCSEL0 bit in SRAMCR to 0.
0: Basic bus interface or byte control SRAM interface
1: Burst ROM interface
0 R/W Area 0 Burst Cycle Select
0 R/W Specifies the number of burst cycles of area 0
0 R/W 000: 1 cycle
001: 2 cycles
010: 3 cycles
011: 4 cycles
100: 5 cycles
101: 6 cycles
110: 7 cycles
111: 8 cycles
All 0 R Reserved
These are read-only bits and cannot be modified.
12 11

BSTS00
0 0
R/W R
4 3

BSTS10
0 0
R/W R
10 9

BSWD01 BSWD00
0 0
R R/W R/W
2 1

BSWD11 BSWD10
0 0
R R/W R/W
8
0
0
0