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14.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Receive data is latched at the middle of each bit by sampling the data at
the rising edge of the 8th pulse of the basic clock as shown in figure 14.3. Thus the reception
margin in asynchronous mode is given by formula (1) below.
1
M = { (0.5 –
) – (L – 0.5) F –
2N
Where M: Reception Margin
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula
below.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
0
Internal base
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 14.3 Receive Data Sampling Timing in Asynchronous Mode
Rev. 2.00, 05/03, page 542 of 820
D – 0.5
N
16 clocks
8 clocks
7
Start bit
(1 + F) }
100 [%]
15 0
D0
... Formula (1)
7
15 0
D1
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