Receive Data Sampling Timing And Reception Margin In Asynchronous Mode; Figure 14.20 Receive Data Sampling Timing In Asynchronous Mode - Renesas H8 Series Hardware Manual

14.8.4

Receive Data Sampling Timing and Reception Margin in Asynchronous Mode

In asynchronous mode, SCI3 operates on a basic clock with a frequency of 16 times the transfer
rate. In reception, SCI3 samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the
basic clock as shown in figure 14.20. Thus, the reception margin in asynchronous mode is given
by formula (1) below.

M = (0.5 – 

Legend N : Ratio of bit rate to clock (N = 16)
D : Clock duty (D = 0.5 to 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
Internal basic
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing

Figure 14.20 Receive Data Sampling Timing in Asynchronous Mode

1 D – 0.5
– (L – 0.5) F × 100(%)
) –
2N N
16 clocks
8 clocks
0 7
Start bit
Section 14 Serial Communication Interface 3 (SCI3)



15 0 7
D0
Rev. 3.00 Sep. 14, 2006 Page 237 of 408
... Formula (1)
15 0
D1
REJ09B0105-0300