Serial Data Reception (Asynchronous Mode); Figure 16.11 Example Of Sci Operation In Reception - Renesas H8S/2158 User Manual

16-bit single-chip microcomputer h8s family/h8s/2100 series
Table of Contents

Advertisement

16.4.7

Serial Data Reception (Asynchronous Mode)

Figure 16.11 shows an example of the operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI monitors the communication line, and if a start bit is detected, performs internal
synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR
is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this
time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF
flag remains to be set to 1.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
Start
1
bit
0
D0
RDRF
FER
Figure 16.11 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity,
Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
Data
Parity
Stop
bit
bit
D1
D7
0/1
1
RXI interrupt
request
generated
1 frame
One Stop Bit)
Start
Data
bit
0
D0
D1
D7
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt service routine
Rev. 3.00 Jan 25, 2006 page 427 of 872
Parity
Stop
bit
bit
1
Idle state
0/1
0
(mark state)
ERI interrupt request
generated by framing
error
REJ09B0286-0300

Advertisement

Table of Contents
loading

Table of Contents