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Section 13 Serial Communication Interface (SCI)
13.4.6
Serial Data Reception (Asynchronous Mode)
Figure 13.8 shows an example of the operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI monitors the communication line, and if a start bit is detected, performs internal
synchronization, stores receive data in RSR, and checks the parity bit and stop bit.
2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR
is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this
time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF
flag remains to be set to 1.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt processing routine reads the receive data transferred to
RDR before reception of the next receive data has finished, continuous reception can be
enabled.
Start
bit
1
0
RDRF
FER
Figure 13.8 Example of SCI Operation for Reception
Rev.2.00 Jun. 28, 2007 Page 488 of 666
REJ09B0311-0200
Data
Parity
bit
D0
D1
D7
0/1
RXI interrupt
request
generated
1 frame
(Example with 8-Bit Data, Parity, One Stop Bit)
Stop
Start
Data
bit
bit
1
0
D0
D1
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt processing routine
Parity
Stop
bit
bit
1
Idle state
D7
0/1
0
(mark state)
ERI interrupt request
generated by framing
error
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