Setting Sscg-Pll Operation Mode With Pins - Renesas PFESiP/V850EP1 User Manual

2.3 Setting SSCG-PLL Operation Mode with Pins

To set SSCG-PLL Operation mode, PFESiP/V850EP1 has the following pins.
Set the following pins to satisfy the specified operating conditions before turning on power.
Pin Name Internal Signal
PLL0-PLL6 PLLM0-PLLM6
PLL7-PLL9 PLLN0-PLLN2
PLL10-PLL11 PLLP0-PLLP1
PLL12-PLL13 SSMDL0-SSMDL1
PLL14-PLL16 SSADJ0-SSADJ2
PLL17-PLL18 PLLS0-PLLS1
CHAPTER 2 INTERNAL SSCG-PLL CHARACTERISTICS
Setting internal PLL multiple rate
m = PLLM0-PLLM6 setting value (0 to 127) + 1
n = PLLN0-PLLN2 setting value (0 to 7) + 92 + 1
PLLP0 to PLLP1 setting value
p = 2
multiple rate = n / m / p
Parameter
Input Frequency
PFD Input Frequency
VCO Output Frequency
Output Frequency
Input Duty
Multiple Rate
Setting SSCG modulation range
SSMDL1 SSMDL0
0 0
0 1
1 0
1 1
Setting SSCG frequency diffusion mode and its range .
SSADJ2 SSADJ1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Inputs SSCG S selector (Frequency Modulation mode)
PLLS1 PLLS0
0 0
0 1
1 0
1 1
User's Manual A19069EJ2V0UM
Function
: 2 to 128
: 93 to 100
: 1, 2, 4
Symbol Formula
f −
std
= f
f f / m
pfd pfd std
= f × n / m
f f
vco vco std
= f × n / m / p
f f
out
out std
I −
duty
MULT MULT = n / m / p
Modulation Period
15.00 to 26.25 kHz (open )
25.00 to 36.75 kHz
35.00 to 48.30 kHz
45.00 to 68.25 kHz
SSADJ0 Frequency Modulation Rate
Approx. − 0.5 %
0
Approx. − 1.0 %
1
Approx. − 2.0 %
0
Approx. − 3.0 %
1
0 Approx. − 4.0 %
1 Approx. − 5.0 %
0 No modulation
1 No modulation
PFD Input Frequency
1.00 MHz ≤ f < 1.20 MHz (open)
pfd
1.20 MHz ≤ f < 1.45 MHz
pfd
1.45 MHz ≤ f < 1.70 MHz
pfd
1.70 MHz ≤ f ≤ 2.00 MHz
pfd
MIN. MAX Unit
2.0 200 MHz
1.0 2.0 MHz
100 200 MHz
25 200 MHz
30 70 %
0.182 50 −
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