Mode Setting With Cascaded Connection; Module Stop Mode Setting - Renesas H8S/2100 Series Hardware Manual

13.9.6

Mode Setting with Cascaded Connection

If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock
pulses for TCNT_0 and TCNT_1, and TCNT_X and TCNT_Y are not generated, and thus the
counters will stop operating. Simultaneous setting of these two modes should therefore be
avoided.
13.9.7

Module Stop Mode Setting

TMR operation can be enabled or disabled using the module stop control register. The initial
setting is for TMR operation to be halted. Register access is enabled by canceling the module stop
mode. For details, see section 26, Power-Down Modes.
Section 13 8-Bit Timer (TMR)
Rev. 1.00 Apr. 28, 2008 Page 389 of 994
REJ09B0452-0100