Mode Setting With Cascaded Connection; Module Stop State Setting; Interrupts In Module Stop State - Renesas H8SX/1650 Hardware Manual

Section 11 8-Bit Timers (TMR)
11.8.7

Mode Setting with Cascaded Connection

If 16-bit counter mode and compare match count mode are specified at the same time, input clocks
for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter
mode and compare match count mode simultaneously.
11.8.8

Module Stop State Setting

Operation of the TMR can be disabled or enabled using the module stop control register. The
initial setting is for operation of the TMR to be halted. Register access is enabled by clearing
module stop state. For details, see section 18, Power-Down States.
11.8.9

Interrupts in Module Stop State

If module stop state is entered when an interrupt has been requested, it will not be possible to clear
the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled
before entering module stop state.
Rev.2.00 Jun. 28, 2007 Page 436 of 666
REJ09B0311-0200