Data Direction Register (Pnddr) (N = 1 To 3, 6, A, D, H, J, And K); Data Register (Pndr) (N = 1 To 3, 6, A, D, H, J, And K) - Renesas H8SX/1520 Series Hardware Manual

Section 8 I/O Ports
8.1.1

Data Direction Register (PnDDR) (n = 1 to 3, 6, A, D, H, J, and K)

DDR is an 8-bit write-only register that specifies the port input or output for each bit. A read from
the DDR is invalid and DDR is always read as an undefined value.
When the general I/O port function is selected, the corresponding pin functions as an output port
by setting the corresponding DDR bit to 1; the corresponding pin functions as an input port by
clearing the corresponding DDR bit to 0.
Bit
Bit Name
Initial Value
R/W
Note: The lower four bits are valid and the upper four bits are reserved for port 2 data direction register (P2DDR).
The lower seven bits are valid and the upper one bit is reserved for port 6 data direction register (P6DDR).
The upper seven bits are valid and the lower one bit is reserved for port A data direction register (PADDR).
8.1.2

Data Register (PnDR) (n = 1 to 3, 6, A, D, H, J, and K)

DR is an 8-bit readable/writable register that stores the output data of the pins to be used as the
general output port.
The initial value of DR is H'00.
Bit
Bit Name
Initial Value
R/W
Note: The lower four bits are valid and the upper four bits are reserved for port 2 data register (P2DR).
The lower seven bits are valid and the upper one bit is reserved for port 6 data register (P6DR).
The upper seven bits are valid and the lower one bit is reserved for port A data register (PADR).
Rev. 3.00 Mar. 14, 2006 Page 212 of 804
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7 6
Pn7DDR Pn6DDR Pn5DDR
0 0
W W
7 6
Pn7DR Pn6DR Pn5DR
0 0
R/W R/W
5 4 3
Pn4DDR Pn3DDR
0 0 0
W W W
5 4 3
Pn4DR Pn3DR
0 0 0
R/W R/W R/W
2 1
Pn2DDR Pn1DDR Pn0DDR
0 0
W W
2 1
Pn2DR Pn1DR Pn0DR
0 0
R/W R/W
0
0
W
0
0
R/W