Register Descriptions; Port A Data Direction Register (Paddr); Port A Data Register (Padr) - Renesas F-ZTAT H8 Series Hardware Manual

11.2

Register Descriptions

11.2.1

Port A Data Direction Register (PADDR)

PADDR is an 8-bit write-only register that selects input or output for each pin in port A.
Bit 7
PA DDR
7
Initial value 0
Read/Write W
Port A is multiplexed with pins TP
be set to 1. For further information about PADDR, see section 9.11, Port A.
11.2.2

Port A Data Register (PADR)

PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when
these TPC output groups are used.
Bit 7
PA
Initial value 0
Read/Write R/(W)
Note: Bits selected for TPC output by NDERA settings become read-only bits.
*
For further information about PADR, see section 9.11, Port A.
6 5
PA DDR PA DDR
6 5
0 0
W W
to TP . Bits corresponding to pins used for TPC output must
7 0
6 5
PA PA
7 6 5
0 0
* R/(W) * R/(W)
Section 11 Programmable Timing Pattern Controller
4 3
PA DDR PA DDR
4 3
0 0
W W
Port A data direction 7 to 0
These bits select input or
output for port A pins
4 3
PA PA
4 3
0 0
* R/(W) * R/(W) *
Port A data 7 to 0
These bits store output data
for TPC output groups 0 and 1
Rev. 7.00 Sep 21, 2005 page 415 of 878
2 1
PA DDR PA DDR PA DDR
2 1
0 0
W W
2 1
PA PA
2 1
0 0
R/(W) * R/(W) * R/(W)
REJ09B0259-0700
0
0
0
W
0
PA
0
0
*