Bit Rate Register (Scbrr); Table 19.2 Scsmr Settings - Renesas HD6417641 Hardware Manual

19.3.8

Bit Rate Register (SCBRR)

The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset.
Each channel has independent baud rate generator control, so different values can be set in three
channels.
The SCBRR setting is calculated as follows:
• Asynchronous mode:
Pφ
N =
64 × 2
2n-1
• Synchronous mode:
Pφ
N =
8 × 2
2n-1
B: Bit rate (bits/s)
SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
N:
Pφ: Operating frequency for peripheral modules (MHz)
Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n:
n, see table 19.2.)

Table 19.2 SCSMR Settings

n
0
1
2
3
Note: The bit rate error in asynchronous is given by the following formula:
Error (%) =
× 10
6
- 1
× B
× 10
6
- 1
× B
Clock Source
Pφ
Pφ/4
Pφ/16
Pφ/64
Pφ × 10
6
(N + 1) × B × 64 × 2
2n-1
Section 19 Serial Communication Interface with FIFO (SCIF)
CKS1
0
0
1
1
× 100
- 1
Rev. 4.00 Sep. 14, 2005 Page 707 of 982
SCSMR Settings
CKS0
0
1
0
1
REJ09B0023-0400