Transfer From Usb Fifo To Serial Sound Interface - Renesas M16C Series User Manual

M30245 Group

3.7 Transfer from USB FIFO to Serial Sound Interface

Overview
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Specifications
Operation
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
The M30245 group, by use of DMAC, transfers data from the USB endpoint 1 OUT FIFO to SS
interface 1 transmit buffer register and fetches one packet data.
The block diagram is shown in Figure 3.7.1 and the setting routine is shown in Figure 3.7.2 to
Figure 3.7.4.
The peripheral functions to be used are as follows:
• DMAC 1 channel
• USB endpoint 1 OUT (Receive)
• Serial sound interface 1
(1) Receive packet data of the endpoint 1 OUT FIFO are transferred to SS interface 1 transmit
buffer register. Transfer is executed every time the DMA transfer factor of the serial sound
interface 1 occurs.
(2) Use the DMA0 to transfer data from the endpoint 1 OUT FIFO to SS interface 1 transmit buffer
register. Select the serial sound interface 1 transmit to the DMA0 request factor. Select the
single transfer mode and set the DMA0 transfer counter to 1/2
packet received with endpoint 1 OUT) –1.
(3) Set the endpoint 1 OUT maximum packet size to 288 bytes (when sampling 48KHz/ 24-bit/
stereo) and disable the AUTO_CLR function. The data count of receive packet of endpoint 1
(endpoint 1 OUT write count register) is set to 288 bytes. Endpoint 1 OUT is used in isochro-
nous transfer.
(4) On completing the DMA0 transfer, fetch of one packet data from the endpoint 1 OUT FIFO is
completed by setting CLR_OUT_BUF_RDY bit of endpoint 1 to "1".
(1) Initialize the DMA0 related registers in the state which DMA is disabled and USB DMA0
request register is not selected (in this case, 16-bit transfer).
(2) When the OUT_BUF_STS1 flag of endpoint 1 is set to "1" and packet data receive has been
detected, set the DMA0 transfer counter to the 1/2
(in this application example, 143 value is set).
(3) Set DMA enable bit of DMA0CON to "1" (DMA0 is enabled). Then, the DMA0 transfer request
from the serial sound interface occurs.
(4) When the transfer request is received, the DMA0 transfers the 1st word (16-bit) data from the
endpoint 1 OUT FIFO to the serial sound interface 1. Simultaneously, the content of the
transfer counter is down-counted. Then, the DMA0 transfer request from the serial sound
interface occurs .
(5) As a result of repetition of the above (4), when the DMA0 transfer counter underflow, DMA
enable bit is set to "0" to complete the DMA0 transfer. Simultaneously, the DMA0 interrupt
request occurs. When the DMA0 interrupt request is detected, set CLR_OUT_BUF_RDY bit
of endpoint 1 OUT to "1".
page 316 of 354
3. USB Applications
(the data count of one
(the data count of receive one packet) –1