Reset Control/Status Register (Rstcsr) - Renesas H8SX/1500 Series Hardware Manual

Section 11 Watchdog Timer (WDT)
Bit Bit Name
5 TME

4, 3
2 CKS2
1 CKS1
0 CKS0
Note: * Only 0 can be written to this bit, to clear the flag.
11.2.3

Reset Control/Status Register (RSTCSR)

RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
but not by the WDT internal reset signal caused by WDT overflows.
7
Bit
WOVF
Bit Name
0
Initial Value
R/(W)*
R/W
Note: * Only 0 can be written to this bit, to clear the flag.
Rev. 3.00 Mar. 14, 2006 Page 370 of 804
REJ09B0104-0300
Initial
Value R/W Description
0 R/W Timer Enable
When this bit is set to 1, TCNT starts counting. When this
bit is cleared, TCNT stops counting and is initialized to
H'00.
All 1 R Reserved
These are read-only bits and cannot be modified.
0 R/W Clock Select 2 to 0
0 R/W Select the clock source to be input to TCNT. The overflow
cycle for Pφ = 20 MHz is indicated in parentheses.
0 R/W
000: Clock Pφ/2 (cycle: 25.6 µs)
001: Clock Pφ/64 (cycle: 819.2 µs)
010: Clock Pφ/128 (cycle: 1.6 ms)
011: Clock Pφ/512 (cycle: 6.6 ms)
100: Clock Pφ/2048 (cycle: 26.2 ms)
101: Clock Pφ/8192 (cycle: 104.9 ms)
110: Clock Pφ/32768 (cycle: 419.4 ms)
111: Clock Pφ/131072 (cycle: 1.68 s)
6 5
RSTE —
0 0
R/W R/W
4 3
— —
1 1
R R
2 1
— —
1 1
R R
0
—
1
R